aboutsummaryrefslogtreecommitdiffstats
path: root/host/lib
Commit message (Expand)AuthorAgeFilesLines
* B100: enable_gpif(0) disables FIFO output clock on FX2. this prevents the "st...Nick Foster2012-03-161-2/+2
* usrp: fix from "rev iq correction"Josh Blum2012-03-163-6/+6
* n2x0: adjustment for phase delay over mimo cableJosh Blum2012-03-141-1/+1
* uhd: make atlbase options for msvc buildJosh Blum2012-03-142-4/+16
* uhd: rev iq correction numbers formatJosh Blum2012-03-143-47/+10
* usrp: fix wildcard set for time/clock sourceJosh Blum2012-03-121-2/+2
* uhd: added fullscale option stream argJosh Blum2012-03-112-0/+4
* Make DBSRX* set default bandwidth based on codec rateJason Abele2012-03-112-2/+7
* Fix RSSI measurementJason Abele2012-03-112-18/+4
* usrp1: fix for cordic init, cant do it that way on txJosh Blum2012-02-291-3/+0
* uhd: fix sc16 to sc8 conversion tableJosh Blum2012-02-291-12/+12
* usrp2: device locking tweaksJosh Blum2012-02-291-9/+6
* usrp: reset cordics on init after tick rate updateJosh Blum2012-02-284-0/+33
* uhd: fixed some compile warnings for msvcJosh Blum2012-02-283-3/+3
* cmake:Nicholas Corgan2012-02-281-1/+1
* uhd: fixed send pkt handler, vrt packet type was uninitializedJosh Blum2012-02-271-0/+1
* usrp1: fix to use the db connection type to determine DAC signJosh Blum2012-02-241-2/+10
* usrp1: fix advertised samples per packet in send streamerJosh Blum2012-02-211-1/+2
* usrp2: some tweaks to the device locking logicJosh Blum2012-02-201-6/+9
* usrp2: added retry logic to control packetsJosh Blum2012-02-201-2/+32
* Merge branch 'next'Josh Blum2012-02-1747-344/+1112
|\
| * dsp rework: fix for vita occ trailer packingJosh Blum2012-02-171-1/+1
| * dsp rework: added flusher to vita tx chain on clearJosh Blum2012-02-152-5/+8
| * uhd: added async md user payload and common utilsJosh Blum2012-02-144-45/+88
| * b100: use frame boundary to calculate frame sizeJosh Blum2012-02-142-4/+6
| * b100: reset/reenumerate fx2 for bad endpoint stateJosh Blum2012-02-143-0/+31
| * b100: added transport flushes and moved around reset codeJosh Blum2012-02-143-13/+7
| * dsp rework: minor fix sph, set has time spec for tsf onlyJosh Blum2012-02-141-2/+2
| * uhd: inline time spec accessors for minor improvementJosh Blum2012-02-131-15/+10
| * b100/usrp1: various tweaks for compiler warns and valgrindJosh Blum2012-02-094-9/+10
| * uhd: various tweaks for compiler warns and valgrindJosh Blum2012-02-097-16/+24
| * uhd: fixed sse2 conversion fc32 to sc8_item32_beJosh Blum2012-02-091-2/+2
| * uhd: fixed orc conversion fc32 to sc8_item32_beJosh Blum2012-02-091-1/+1
| * B100: Firmware reset tweaks.Nick Foster2012-02-091-1/+1
| * uhd: added sse2 conversions for fc32 to sc8Josh Blum2012-02-082-0/+151
| * uhd: added sse2 conversions for fc64 to sc8Josh Blum2012-02-084-9/+166
| * Add Orc functions to convert to sc8. bswap version is a bit of a hack.Nick Foster2012-02-082-0/+28
| * uhd: added sc8 conversion testsJosh Blum2012-02-073-3/+72
| * dsp rework: implement 64 bit ticks, no secondsJosh Blum2012-02-0616-87/+86
| * B100: use FPGA external reset on initNick Foster2012-02-062-0/+7
| * b100/e100: unify rx/tx fifo clears into oneJosh Blum2012-02-044-14/+8
| * b100: delete some unused registers from mapJosh Blum2012-02-042-7/+0
| * dsp rework: move setting address of format registerJosh Blum2012-02-022-6/+4
| * dsp rework: work on usb wrapper for smaller packets, large lutsJosh Blum2012-02-0215-80/+105
| * b100: sc8 mode not implemented errorJosh Blum2012-02-011-0/+4
| * b100: bump compat numbers for slave fifo modeJosh Blum2012-02-011-1/+1
| * B100: Modified TX send size to achieve 10.7Msps.Nick Foster2012-02-011-1/+1
| * B100 host code changes to remove TX padding, remove RX padding, increase max ...Nick Foster2012-02-012-3/+3
| * dsp rework: account for no sid used in tx vita pktJosh Blum2012-02-013-1/+4
| * dsp rework: tx trailer, scaling work (peak)Josh Blum2012-01-3110-27/+105
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-15 22:05:14 +0000