| Commit message (Collapse) | Author | Age | Files | Lines |
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This allows to read a relative temperature from an AD9361 device.
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Conflicts:
host/include/uhd/types/direction.hpp
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Conflicts:
host/include/uhd/types/CMakeLists.txt
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* Added CMake toolchain file, compatible with different versions
* No dependency on MinGW runtime, all statically linked
* Misc coding tweaks to allow MinGW to compile
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Conflicts:
host/examples/rx_samples_to_file.cpp
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- Bugfix for #638
- get_ref_locked will check lock status one last time before giving up
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Our VRT routines have the option to switch, on the fly, between
VRLP and CHDR. This adds new CHDR-specific (un-)packers, which
can only work with CHDR.
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- Deleted images.*, moved functionality to paths.*
- Applies for all devices that check FPGA or FW compat numbers
- Adds generic utility search tool
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Conflicts:
host/lib/usrp/b200/b200_impl.hpp
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When no master_clock_rate is defined, the B200 driver will now
select a suitable clock rate automatically based on the selected
sampling rate.
The selected tick rate is a multiple of the LCM of tx and rx rates.
Auto-setting is done every time a streamer is generated or the sampling
rate is configured.
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- DAC: Squashed configuration into 2 main operations: reset and reset_and_resync
- DAC: Put in sleep mode during configuration
- DAC: Synchronize only if streaming to more than one DAC
- DAC: Use falling edge sync mode
- DAC: Fixed power up/down settings
- DAC: Frontend sync failure is fatal
- Clocks: Refactored clock source change logic
- Clocks: Cleaned up init and lock-check sequence
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This is a data type to represent SIDs (stream IDs).
It includes setters and getters for all components of the
SID, converters to and from string and uint32 as well
as C++ streams.
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- Switched DAC to DCI delay bypass mode because we
shift the DCI in the FPGA now
- Changed LMK control to add 900ps delay to DAC clocks
to be consistent with the radio_clk delay. The timing
analyzer is expecting the two clocks to have a 0 deg
phase diff.
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- Refactored SFP+ hotplug handler
- GigE link state comes from SFP+ status and PHY status
- Multiple tracing enhancements
- Bumped firmware compat number to 4
- Bumpled FPGA compat number to 10
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This is a renaming of the previously created $UHDCALIBPATH.
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Also added new enviornment variable, "UHDCALIBPATH", so that users can
use something other than system-required environment paths.
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Also includes NI-USRP Windows Registry Key fixes.
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- Fix ported from He. The current TX filter does not need
the additional -6dB of headroom. Set it to zero so we
meet our max power specs.
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- The control bits for the small and the large half-bands were swapped which would cause the large HB to run too fast. Swapped hb0 and hb1 bits to fix the issue.
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