x300: Timing changes for the new DAC data interface

- Switched DAC to DCI delay bypass mode because we
  shift the DCI in the FPGA now
- Changed LMK control to add 900ps delay to DAC clocks
  to be consistent with the radio_clk delay. The timing
  analyzer is expecting the two clocks to have a 0 deg
  phase diff.

2 files changed, 16 insertions, 7 deletions

diff --git a/host/lib/usrp/x300/x300_clock_ctrl.cpp b/host/lib/usrp/x300/x300_clock_ctrl.cpp
index 247c10ac4..22eba3eb3 100644
--- a/host/lib/usrp/x300/x300_clock_ctrl.cpp
+++ b/host/lib/usrp/x300/x300_clock_ctrl.cpp
@@ -287,6 +287,8 @@ void set_master_clock_rate(double clock_rate) {
     this->write_regs(0);
     _lmk04816_regs.CLKout0_1_DIV = vco_div;
     _lmk04816_regs.CLKout0_ADLY_SEL = lmk04816_regs_t::CLKOUT0_ADLY_SEL_D_EV_X;
+    _lmk04816_regs.CLKout6_ADLY_SEL = lmk04816_regs_t::CLKOUT6_ADLY_SEL_D_BOTH;
+    _lmk04816_regs.CLKout7_ADLY_SEL = lmk04816_regs_t::CLKOUT7_ADLY_SEL_D_BOTH;
     this->write_regs(0);
 
     // Register 1
@@ -309,9 +311,12 @@ void set_master_clock_rate(double clock_rate) {
     _lmk04816_regs.CLKout1_TYPE = lmk04816_regs_t::CLKOUT1_TYPE_P_DOWN; //CPRI feedback clock, use LVDS
     _lmk04816_regs.CLKout2_TYPE = lmk04816_regs_t::CLKOUT2_TYPE_LVPECL_700MVPP; //DB_0_RX
     _lmk04816_regs.CLKout3_TYPE = lmk04816_regs_t::CLKOUT3_TYPE_LVPECL_700MVPP; //DB_1_RX
-    // Analog delay of 900ps to synchronize the radio clock with the source synchronous ADC clocks.
+    // Delay the FPGA_CLK by 900ps to ensure a safe ADC_SSCLK -> RADIO_CLK crossing.
+    // If the FPGA_CLK is delayed, we also need to delay the reference clocks going to the DAC
+    // because the data interface clock is generated from FPGA_CLK.
     // This delay may need to vary due to temperature.  Tested and verified at room temperature only.
     _lmk04816_regs.CLKout0_1_ADLY = 0x10;
+    _lmk04816_regs.CLKout6_7_ADLY = _lmk04816_regs.CLKout0_1_ADLY;
 
     // Register 7
     _lmk04816_regs.CLKout4_TYPE = lmk04816_regs_t::CLKOUT4_TYPE_LVPECL_700MVPP; //DB_1_TX
diff --git a/host/lib/usrp/x300/x300_dac_ctrl.cpp b/host/lib/usrp/x300/x300_dac_ctrl.cpp
index d3bcb8644..bb41146b6 100644
--- a/host/lib/usrp/x300/x300_dac_ctrl.cpp
+++ b/host/lib/usrp/x300/x300_dac_ctrl.cpp
@@ -129,12 +129,16 @@ public:
         _check_pll();
 
         // Configure digital interface settings
-        write_ad9146_reg(0x16, 0x02); // Skew DCI signal by 615ps to find stable data eye
-        write_ad9146_reg(0x03, 0x00); // 2's comp, I first, byte wide interface
-        //fpga wants I,Q in the sample word:
-        //first transaction goes into low bits
-        //second transaction goes into high bits
-        //therefore, we want Q to go first (bit 6 == 1)
+        // Bypass DCI delay. We center the clock edge in the data
+        // valid window in the FPGA by phase shifting the DCI going
+        // to the DAC.
+        write_ad9146_reg(0x16, 0x04);
+        // 2's comp, I first, byte wide interface
+        write_ad9146_reg(0x03, 0x00);
+        // FPGA wants I,Q in the sample word:
+        // - First transaction goes into low bits
+        // - Second transaction goes into high bits
+        //   therefore, we want Q to go first (bit 6 == 1)
         write_ad9146_reg(0x03, (1 << 6)); //2s comp, i first, byte mode
 
         // Configure interpolation filters