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| * UBX: Phase synchronizationmichael-west2016-02-184-3/+9
| | | | | | | | | | | | | | - Disabled MAX2871 VCO auto selection for phase sync - Added checks for new phase sync constraints recently published by Maxim - Added dboard_clock_rate option for X300 - Adjusted timing of SYNC signal relative to dboard referenc clock
* | x300: Added capability to write_spi to BOTH channels in dboard_ifaceAshish Chaudhari2016-02-181-6/+8
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* | x300,e300: Fixed IQ swapping issue in RX frontendAshish Chaudhari2016-02-171-6/+2
| | | | | | | | - DB connection mapping is implemented in DDC chain. FE corrections module does not swap
* | usrp: Refactored dboard_iface for all productsAshish Chaudhari2016-02-161-41/+52
| | | | | | | | | | | | | | - Made dboard_iface an interface! Removed PIMPL - Added unit "BOTH" to dboard API and expanded GPIO API width to 32 - Removed gpio_debug_mux. No product ever used that - Refactored gpio_atr cores to work with new dboard_iface
* | dboard: Added restricted dboard registration capabilityAshish Chaudhari2016-02-162-4/+1
| | | | | | | | | | | | - Moved dboard iface initialization to dboard_manager - Added a restricted register function. Restricted dboards don't expose their control iface in the property tree
* | prop_tree: Multiple API enhancements to uhd::propertyAshish Chaudhari2016-02-111-30/+30
| | | | | | | | | | | | | | | | | | - Added desired and coerced values and accessors to property - Added support to register desired subscribers - set APIs don't reallocate storage for a property value - Renamed callback method registration APIs - Registering 2 coercers or publishers for a property will throw - Registering a coercer and a publisher for the same property will throw
* | bugfix#366: X300: PCIe: Live load of firmware failsAshish Chaudhari2016-01-111-0/+2
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* | b2xx,e3xx,x300: Bumped FPGA compat numbers after incompatible maint mergeAshish Chaudhari2015-12-151-1/+1
| | | | | | | | | | | | | | - b200: compat 14 - b200mini: compat 5 - e3xx: compat 15 - x3xx: compat 20
* | Merge branch 'maint'Ashish Chaudhari2015-12-154-3/+14
|\| | | | | | | | | | | | | Conflicts: host/lib/usrp/b200/b200_impl.hpp host/lib/usrp/e300/e300_fpga_defs.hpp host/lib/usrp/x300/x300_fw_common.h
| * b2xx,e3xx,x300: Bumped FPGA compat numbers after SW time-sync changesAshish Chaudhari2015-12-101-1/+1
| | | | | | | | | | | | | | - b200: compat 13 - b200mini: compat 4 - e3xx: compat 14 - x3xx: compat 19
| * Bumped FPGA compat numbers for B200, X300, and E300.michael-west2015-12-101-1/+1
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| * E300/X300: Add VITA time synchronization on internal signalmichael-west2015-12-103-2/+13
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| * b2xx,e3xx,x300: Bumped compat numbers for 3.9.1 UHD releaseAshish Chaudhari2015-09-031-1/+1
| | | | | | | | | | | | | | - b200: compat 11 - b200mini: compat 2 - e300: compat 11 - x300: compat 15
| * cores: Corrected scaling_adjustment calculationIan Buckley2015-09-032-0/+10
| | | | | | | | | | | | Compensate for headroom required to rotate a signal in the CORDIC. Fixes some CORDIC-related clipping issues, that reduced ENOB to 15 or 14.5 bits.
* | x3xx,e3xx: Bumped FPGA compat number after register overlap fixAshish Chaudhari2015-11-241-1/+1
| | | | | | | | | | - e300: compat 13 - x300: compat 18
* | radio: Fixed overlapping register for LED and FPGPIO coreAshish Chaudhari2015-11-241-1/+1
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* | cmake: Register components earlierMartin Braun2015-11-161-2/+0
| | | | | | | | | | | | | | | | | | | | All device-specific CMake components are now registered in one place, before the host/lib/ subdirs are sourced. This way, there are no cyclic dependencies. This solves the issue where ENABLE_X300=Off could disable USB, but preserves the fix where ENABLE_X300=Off would still build some X300 codes.
* | b2xx,e3xx,x300: Bumped compat numbers after GPIO ATR refactoringAshish Chaudhari2015-10-161-1/+1
| | | | | | | | | | | | | | - b200: compat 12 - b200mini: compat 3 - e300: compat 12 - x300: compat 17
* | Merge branch 'ashish/gpio_atr_redux' into master-stagingAshish Chaudhari2015-10-152-41/+17
|\ \ | | | | | | | | | | | | | | | Conflicts: host/lib/usrp/cores/CMakeLists.txt host/lib/usrp/x300/x300_impl.hpp
| * | usrp3: Added new GPIO ATR 3000 coreAshish Chaudhari2015-09-292-41/+17
| | | | | | | | | | | | | | | | | | | | | | | | - Refactored GPIO ATR definitions - Added new 3000 core with a more efficient API - Added a separate db_gpio_atr core to control the ATR bus - Ported b2xx, e3xx and x3xx to the new core - Minor cleanup
* | | fixup! x300: Added DMA FIFO support to X300Ashish Chaudhari2015-09-301-1/+1
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* | | x300: Bumped FPGA compat number to 16Ashish Chaudhari2015-09-161-1/+1
| | | | | | | | | | | | - New and improved DRAM DMA FIFO
* | | x300: Made DRAM FIFO size software configurableAshish Chaudhari2015-09-162-0/+3
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* | | x300: Added DMA FIFO support to X300Ashish Chaudhari2015-09-164-18/+75
|/ / | | | | | | | | - Added HG vs HGS detection logic - Added DMA FIFO configuration code
* | b2xx,e3xx,x300: Bumped compat numbers for 3.9.1 UHD releaseAshish Chaudhari2015-09-081-1/+1
| | | | | | | | | | | | | | - b200: compat 11 - b200mini: compat 2 - e300: compat 11 - x300: compat 15
* | cores: Corrected scaling_adjustment calculationIan Buckley2015-09-082-0/+10
|/ | | | | | Compensate for headroom required to rotate a signal in the CORDIC. Fixes some CORDIC-related clipping issues, that reduced ENOB to 15 or 14.5 bits.
* X300: Fix base address for FP GPIOmichael-west2015-09-011-1/+1
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* x300: Removed call to is_pps_presentAshish Chaudhari2015-08-171-4/+4
| | | | - It's status is thrown away anyway
* b200,e300,x300: Updated compat number for release 3.9.0Ashish Chaudhari2015-08-141-1/+1
| | | | | | - b200: compat 10 - e300: compat 10 - x300: compat 14
* uhd: Fixes to build with MSVCAshish Chaudhari2015-08-131-1/+1
| | | | | - Included list header in soft_reg header - Fixed typo in x300_impl
* B200/X300: Make default clock and time sources internalmichael-west2015-08-121-14/+0
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* UHD: Remove initialization of time to GPS time.michael-west2015-08-121-4/+1
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* Merge branch 'master' into ashish/register_apiAshish Chaudhari2015-08-121-1/+1
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| * cmake: added variable to LIBUHD_REGISTER_COMPONENT macro to make required, ↵Nicholas Corgan2015-08-111-1/+1
| | | | | | | | | | | | set LibUHD to required * If required component's dependencies aren't met, CMake will throw an error unless user specifically disables it
* | Merge branch 'master' into ashish/register_apiAshish Chaudhari2015-08-104-58/+80
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| * x300: added missing included necessary in Boost 1.46Nicholas Corgan2015-08-101-0/+1
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| * x300, e300: Moved common register names to radio namespaceMartin Braun2015-08-074-48/+55
| | | | | | | | This preps the code for merging common registers altogether.
| * image_loader: force user to specify deviceNicholas Corgan2015-08-051-9/+23
| | | | | | | | | | * On utility level, force user to use --args=type=foo * In each loader, throw an error if args are ambiguous
| * x300: nirio: Fix compiler warningsMoritz Fischer2015-07-311-1/+1
| | | | | | | | | | | | | | | | | | The old code used a non standard (though very common) way to determine the size of an array. In order to avoid warnings, pass another parameter to indicate the size. Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
* | x300: Used new soft register API for X300 registersAshish Chaudhari2015-08-044-176/+196
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* x300: Moved all tick set subscribers to same placeMartin Braun2015-07-291-10/+7
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* cores: Moved subtree populate code to DSP cores (X3x0, E310)Martin Braun2015-07-291-36/+26
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* cores: Moved subtree populate code to frontend coresMartin Braun2015-07-291-20/+8
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* x300: Updated FPGA->ADC Clock delays for all boardsAshish Chaudhari2015-07-241-2/+2
| | | | - Delays changed after ADC config change and FPGA fixes
* x300: Removed radio_rst assertion codeAshish Chaudhari2015-07-233-3/+4
| | | | | | - radio_rst was being asserted to reset the capture iface IDELAYs but that was excessive and had adverse effects on the rest of the radio - Replaced radio_rst with a localized IDELAYCTRL reset
* Revert "x300: Changed ADC clock swing to 1.6V from 0.7V"Ashish Chaudhari2015-07-231-2/+2
| | | | This reverts commit a12b24027fe1af9ca51949f6a9333ac5451690ef.
* x300: Moved system-level ADC and DAC operationsAshish Chaudhari2015-07-233-386/+413
| | | | | | | | | | | - The following function implementations were moved from x300_impl.cpp to x300_adc_dac_utils.cpp - synchronize_dacs - self_test_adcs - extended_adc_test - self_cal_adc_capture_delay - self_cal_adc_xfer_delay - This reduces the size of the x300_impl object file
* x300: Increased the max image size for burnerAshish Chaudhari2015-07-231-1/+1
| | | | - We added additional microcode to configure DCI matching,config rate,etc
* x300: Updated CLK->DATA delay for ADCAshish Chaudhari2015-07-221-2/+2
| | | | | | | | - The value was originally empirically determined based on self-cal results. After the fix for uncalibrated IDELAY, the self-cal offset data was no longer correct. - The new delay through the ADC ensures that the self-cal nominally pick the halfway tap of 16
* x300: Added a comprehensive radio reset sequenceAshish Chaudhari2015-07-224-32/+68
| | | | | | | | | | | - Everytime the LMK is configured, we do the following: - Reset all LMK regs - Wait for LMK lock - Reset radio_clk PLL in FPGA - Wait for FPGA PLL to lock - Assert radio_rst which resets downstream radio logic - This address the intermittent self-cal failures due to uncalibrated IDELAY taps - Bumped FPGA compat to 12
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