| Commit message (Collapse) | Author | Age | Files | Lines |
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- Self-calibration routine steps through various values of IDELAY
taps on the SS data bits to detect metastability in the capture interface
and computes an ideal delay tap value
- Self calibration is triggered at device creation
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- Self-calibration routine steps through various values of LMK
delay to detect metastability in the SSCLK -> radio_clk crossing
and computes an ideal delay for the ADC clock.
- Self calibration is triggered at startup if the self_cal_adc_delay
device arg is specified
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- This function allows delaying divider pairs using the digital and analog
delay blocks in the LMK divider
- ctrl object caches delay for later retrieval
- Minor fixes to LMK regmap
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Conflicts:
host/lib/usrp/common/ad9361_ctrl.hpp
host/lib/usrp/common/ad9361_driver/ad9361_device.h
host/lib/usrp/e300/e300_remote_codec_ctrl.hpp
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- The firmware is a subset of the FPGA so this order makes sense
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Conflicts:
host/lib/usrp/x300/x300_clock_ctrl.cpp
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This creates a wb_iface child class called timed_wb_iface, which
adds support for timed commands.
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Conflicts:
host/docs/usrp_e3x0.dox
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- Increased filter loop bandwith on clock control chip
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* CMake now not applying C++ flags to C files
* GCC 4.4: anti-aliasing rules
* MSVC: narrowing, differences in subclass function parameters
* Clang: uninitialized variables
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- GPIO on UART connector all board Revs
- Consolidated fpgpio_bitbang into fpgpio example and renamed it gpio
- Changed FP_GPIO readback address to match X300
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- Bugfix for #638
- get_ref_locked will check lock status one last time before giving up
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- Deleted images.*, moved functionality to paths.*
- Applies for all devices that check FPGA or FW compat numbers
- Adds generic utility search tool
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- Switched DAC to DCI delay bypass mode because we
shift the DCI in the FPGA now
- Changed LMK control to add 900ps delay to DAC clocks
to be consistent with the radio_clk delay. The timing
analyzer is expecting the two clocks to have a 0 deg
phase diff.
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- Refactored SFP+ hotplug handler
- GigE link state comes from SFP+ status and PHY status
- Multiple tracing enhancements
- Bumped firmware compat number to 4
- Bumpled FPGA compat number to 10
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Also includes NI-USRP Windows Registry Key fixes.
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- Moved setting of tick rate before setting of PPS time
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- X300: FPGA compat 9
- E300: FPGA compat 5
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- DAC: Squashed configuration into 2 main operations: reset and reset_and_resync
- DAC: Put in sleep mode during configuration
- DAC: Synchronize only if streaming to more than one DAC
- DAC: Use falling edge sync mode
- DAC: Fixed power up/down settings
- DAC: Frontend sync failure is fatal
- Clocks: Refactored clock source change logic
- Clocks: Cleaned up init and lock-check sequence
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- Split niriok_proxy interfaces to support NI-RIO <=13.0 and >=14.0 kernel interfaces
- Fixed multi-session race conditions by synchronizing niriok_proxy access
- Fixed bug switching from NI LV-FPGA access to UHD access by changing how devices are hashed into a reservation table
- Fixed calculation of FRAC values for CBX and SBX LO tuning by rounding instead of truncating
- Fixed bug that was not setting two MSBs for band select configuration of CBX LO
- Submitting on behalf of Patrick Sisterhen, Matthew Crymble
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- Trading performance for stability. This helps meet timing at the cost of a shorter processing time window between sends.
- Bumped FPGA compat number to 8
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* Add "ignore-cal-file" to the uhd::device_addr_t arguments
* Added documentation for new feature
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