| Commit message (Collapse) | Author | Age | Files | Lines |
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This pulls out a lot of code from x300_impl and puts it into its own
compilation units:
- EEPROM code goes to x300_mb_eeprom.*
- Claim code goes to x300_claim.*
- PCIe code goes to uhd::usrp::x300::pcie_manager
- Ethernet code goes to uhd::usrp::x300::eth_manager
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Use dpdk_simple together with a control transport factory.
Where udp_zero_copy is used, use dpdk_zero_copy if use_dpdk=1.
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- ADC self test had magic numbers for default duration
- resource and addr can be no longer be both specified without a warning
- second_addr requires addr now, or you get a warning
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Before, it was only returning the master clock rate. Note: This function
is never used in UHD, this is merely for completion's sake.
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Applying formatting changes to all .cpp and .hpp files in the following
directories:
```
find host/examples/ -iname *.hpp -o -iname *.cpp | \
xargs clang-format -i -style=file
find host/tests/ -iname *.hpp -o -iname *.cpp | \
xargs clang-format -i -style=file
find host/lib/usrp/dboard/neon/ -iname *.hpp -o -iname *.cpp | \
xargs clang-format -i -style=file
find host/lib/usrp/dboard/magnesium/ -iname *.hpp -o -iname *.cpp | \
xargs clang-format -i -style=file
find host/lib/usrp/device3/ -iname *.hpp -o -iname *.cpp | \
xargs clang-format -i -style=file
find host/lib/usrp/mpmd/ -iname *.hpp -o -iname *.cpp | \
xargs clang-format -i -style=file
find host/lib/usrp/x300/ -iname *.hpp -o -iname *.cpp | \
xargs clang-format -i -style=file
find host/utils/ -iname *.hpp -o -iname *.cpp | \
xargs clang-format -i -style=file
find mpm/ -iname *.hpp -o -iname *.cpp | \
xargs clang-format -i -style=file
```
Also formatted host/include/, except Cpp03 was used as a the language
standard instead of Cpp11.
```
sed -i 's/ Cpp11/ Cpp03/g' .clang-format
find host/include/ -iname *.hpp -o -iname *.cpp | \
xargs clang-format -i -style=file
```
Formatting style was designated by the .clang-format file.
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Add a new clocking mode to automatically configure arbitrary master
clock rates.
Co-authored-by: Brent Stapleton <brent.stapleton@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
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UHD currently only uses a single ethernet link for tx data, even if the
device is initialized with dual 10GbE links. Using both links when a DMA
FIFO is present causes sequence errors due to DMA FIFO bandwidth
limitations. This maintains the current default behavior but allows
users to override it through a device arg "enable_tx_dual_eth".
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None of our FPGA images support a 120 MHz master clock rate, so the UHD
code should match that.
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x300_impl will now use a constrained_device_args_t-derived object to
parse device args.
No API or functional changes.
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