| Commit message (Collapse) | Author | Age | Files | Lines |
|---|
| |
|
|
|
|
|
| |
All copyright is now attributed to "Ettus Research, a National
Instruments company".
SPDX headers were also updated to latest version 3.0.
|
| | |
|
| |
|
|
|
| |
Reviewed-by: Martin Braun <martin.braun@ettus.com>
Reviewed-by: Ashish Chaudhari <ashish.chaudhari@ettus.com>
|
| | |
|
| |
|
|
|
| |
Note: This is the first commit that uses for-range, and range-based
for-loops are now usable for UHD development.
|
| |
|
|
|
|
|
|
| |
types)
- Also removes all references to boost/cstdint.hpp and replaces it with
stdint.h (The 'correct' replacement would be <cstdint>, but not all of our
compilers support that).
|
| | |
|
| |
|
|
|
|
|
| |
- The spectral distortion was begin caused by the DAC FIFO
underflowing. The fix was to run through the DAC sync
procedure which uses the falling edge clock to sample
the RefClk and sync it with the data clk
|
| |
|
|
|
|
|
|
|
| |
- Switched DAC to DCI delay bypass mode because we
shift the DCI in the FPGA now
- Changed LMK control to add 900ps delay to DAC clocks
to be consistent with the radio_clk delay. The timing
analyzer is expecting the two clocks to have a 0 deg
phase diff.
|
| |
|
|
|
|
|
|
|
|
|
| |
- DAC: Squashed configuration into 2 main operations: reset and reset_and_resync
- DAC: Put in sleep mode during configuration
- DAC: Synchronize only if streaming to more than one DAC
- DAC: Use falling edge sync mode
- DAC: Fixed power up/down settings
- DAC: Frontend sync failure is fatal
- Clocks: Refactored clock source change logic
- Clocks: Cleaned up init and lock-check sequence
|
| |\ |
|
| | | |
|
| |/ |
|
| |
|
