uhd - Ettus' UHD Repository

	Commit message (Collapse)	Author	Age	Files	Lines
*	ad9361: Renamed ad9361_impl.c to ad9361_device.cpp	Ashish Chaudhari	2014-08-12	1	-6/+1
\|
*	b200, ad9361: Cleanup up AD9361 driver	Ashish Chaudhari	2014-08-12	1	-2/+0
\| \| \| \| \|	- Removed transaction interface - Made the driver a C++ class
*	b200: Moved AD9361 driver to host	Ashish Chaudhari	2014-08-01	1	-0/+9
\| \| \| \| \| \| \|	- Switched to FPGA SPI engine - Moved firmware AD9361 driver to UHD - Bumped FW compat to 5, FPGA compat to 4 - Known Issue: AD9361 SPI rate is too slow
*	120 MHz daughterboard support, Integer-N tuning, ADF435x code consolidation	Nicholas Corgan	2014-01-24	1	-0/+1
\| \| \| \| \| \| \|	* Added support for new CBX-120, SBX-120, and WBX-120 daughterboards * Added implementation of Integer-N tuning for all CBX, SBX, and WBX daughterboards * Added --int-n option to examples to show how to use Integer-N tuning API * Removed duplicate ADF4350/ADF4351 code and moved it to common/adf435x_common.cpp
*	uhd: squashed support modules for usrp3 fpga cores	Josh Blum	2013-07-19	1	-1/+3
\|
*	usrp: added fifo_ctrl_excelsior for FIFO control + async msgs	Josh Blum	2012-07-02	1	-1/+2
\| \| \| \| \| \|	The fifo_ctrl_excelsior is the host code for dealing with E100/B100 control messages and async messages. It also has the SPI implementation. Timed commands are implemented on top of this code.
*	usrp: basically working iq cal on tx	Josh Blum	2011-11-10	1	-0/+1
\|
*	usrp: created common code to demux an rx stream (b100, e100)	Josh Blum	2011-07-01	1	-2/+7
\|
*	usrp: added validate_subdev_spec to all io_impls	Josh Blum	2011-07-01	1	-1/+1
\|
*	usrp: moved fx2 stuff into common folder	Josh Blum	2011-07-01	1	-0/+29