| Commit message (Expand) | Author | Age | Files | Lines |
* | fpga: rfnoc: Remove rfnoc_version from target YAML | Wade Fife | 2022-06-10 | 14 | -14/+0 |
* | fpga: x400: Increase replay SEP buffer sizes | Wade Fife | 2022-04-06 | 6 | -28/+28 |
* | fpga: x400: Add timed commands support for all radio ctrlport endpoints | Javier Valenzuela | 2022-04-04 | 7 | -182/+104 |
* | fpga: Update all RFNoC images | Wade Fife | 2022-03-31 | 29 | -468/+508 |
* | rfnoc: Update device port names in image core YAML | Wade Fife | 2022-03-31 | 14 | -654/+767 |
* | fpga: n3xx: Add missing BIST image core headers | Wade Fife | 2022-03-29 | 6 | -45/+108 |
* | fpga: Use PROTOVER and CHDR_W from RFNoC image builder | Wade Fife | 2022-03-29 | 13 | -27/+113 |
* | fpga: n3xx: Fix clock frequency comments | Wade Fife | 2022-03-26 | 1 | -2/+2 |
* | fpga: e31x: Update DRAM IP simulation | Wade Fife | 2022-03-23 | 1 | -4/+22 |
* | fpga: e31x: Fix DRAM traffic gen IP name | Wade Fife | 2022-03-23 | 1 | -1/+1 |
* | fpga: x400: Add x410_400_128_rfnoc_image_core | Wade Fife | 2022-03-14 | 5 | -3/+1613 |
* | fpga: x400: Cleanup FPGA Makefile | Wade Fife | 2022-03-04 | 1 | -40/+61 |
* | fpga: x400: Add support for DRAM with 400 MHz BW | Wade Fife | 2022-03-04 | 2 | -22/+24 |
* | fpga: x400: Change AXI XB for DRAM to 512-bit | Wade Fife | 2022-03-04 | 1 | -106/+17 |
* | fpga: x400: Add SPI Controller Info register | Javier Valenzuela | 2022-03-04 | 6 | -11/+156 |
* | fpga: x400: Adjust SPI engine strobes alignment | Javier Valenzuela | 2022-03-04 | 4 | -9/+14 |
* | fpga: x400: Set replay SEP buffers to twice MTU | Wade Fife | 2022-02-24 | 2 | -8/+8 |
* | Remove FSRU-related files | Martin Braun | 2022-02-22 | 1 | -1/+0 |
* | fpga: e320: Add DRAM ports | Wade Fife | 2022-02-18 | 1 | -97/+97 |
* | fpga: n3xx: Fix DRAM FIFO address alignment | Wade Fife | 2022-02-10 | 3 | -6/+6 |
* | fpga: e31x: Add DRAM support | Wade Fife | 2022-02-10 | 15 | -99/+1499 |
* | fpga: x400: Add DRAM enable macro | Javier Valenzuela | 2022-02-10 | 1 | -0/+4 |
* | fpga: b2xx: Generate utilization report files | Martin Braun | 2022-02-10 | 2 | -18/+24 |
* | fpga: x400: zbx: cpld: Bump ZBX regmap copyright | Javier Valenzuela | 2022-02-10 | 11 | -11/+11 |
* | fpga: x400: cpld: Bump CMI wrapper copyright | Javier Valenzuela | 2022-02-10 | 2 | -2/+2 |
* | fpga: x400: Bump minor version | Wade Fife | 2022-02-07 | 3 | -8/+8 |
* | fpga: x400: Update rfnoc_image_core files | Wade Fife | 2022-02-07 | 8 | -98/+1327 |
* | fpga: x400: Add Replay to 100 and 200 MHz images | Wade Fife | 2022-02-07 | 2 | -36/+107 |
* | fpga: x400: Add DRAM support | Wade Fife | 2022-02-07 | 5 | -106/+1272 |
* | fpga: x400: Set DRAM speed to 2.0 GT/s | Wade Fife | 2022-02-07 | 1 | -26/+26 |
* | fpga: x400: Add axi_inter_4x64_512_bd IP | Wade Fife | 2022-02-07 | 3 | -0/+604 |
* | fpga: x400: Add axi_inter_2x128_512_bd IP | Wade Fife | 2022-02-07 | 3 | -0/+449 |
* | images: Update N32x CPLD manifest | Humberto Jimenez | 2022-01-31 | 1 | -1/+1 |
* | fpga: n3xx: rh: cpld: Refactor CPLD build process | Humberto Jimenez | 2022-01-25 | 6 | -24/+119 |
* | fpga: x400: cpld: Bump copyright | Javier Valenzuela | 2022-01-25 | 9 | -9/+9 |
* | fpga: x400: Bump copyright | Javier Valenzuela | 2022-01-25 | 14 | -14/+14 |
* | fpga: x400: Expand PS GPIO port for DIO control | Javier Valenzuela | 2022-01-25 | 7 | -19/+58 |
* | fpga: x400: Add SPI bus support for GPIO ports | Javier Valenzuela | 2022-01-25 | 9 | -60/+1338 |
* | fpga: x400: Add GPIO control via ATR and DB state | Javier Valenzuela | 2022-01-25 | 14 | -199/+2932 |
* | fpga: x400: Connect Radio Blocks to DIO | Javier Valenzuela | 2022-01-25 | 10 | -305/+626 |
* | fpga: x400: Fix rfnoc_image_core.vh path | Wade Fife | 2022-01-12 | 1 | -1/+1 |
* | fpga: e320: Connect CTRL_IN pins to FPGA | Martin Braun | 2022-01-10 | 2 | -1/+12 |
* | fpga: e320: Remove copy/paste from N310 code | Martin Braun | 2022-01-10 | 1 | -9/+0 |
* | fpga: x300: Fix time register readback | Wade Fife | 2021-12-15 | 1 | -2/+2 |
* | fpga: x300: OR ATR signals going into db_control | Martin Braun | 2021-12-07 | 1 | -1/+10 |
* | fpga: x400: cpld: Add manufacturing support | Humberto Jimenez | 2021-12-01 | 4 | -7/+27 |
* | fpga: x400: Refactor CPLDs build process | Humberto Jimenez | 2021-12-01 | 33 | -254/+733 |
* | x410: correct 100GbE link speed | Andrew Lynch | 2021-11-02 | 2 | -2/+2 |
* | fpga: Shorten line length for Launchpad linter | Aaron Rossetto | 2021-10-28 | 1 | -2/+4 |
* | fpga: x300: Update synchronizer constraint | Wade Fife | 2021-09-13 | 1 | -1/+1 |