| Commit message (Expand) | Author | Age | Files | Lines |
* | images: Update N32x CPLD manifest | Humberto Jimenez | 2022-01-31 | 1 | -1/+1 |
* | fpga: n3xx: rh: cpld: Refactor CPLD build process | Humberto Jimenez | 2022-01-25 | 6 | -24/+119 |
* | fpga: x400: cpld: Bump copyright | Javier Valenzuela | 2022-01-25 | 9 | -9/+9 |
* | fpga: x400: Bump copyright | Javier Valenzuela | 2022-01-25 | 14 | -14/+14 |
* | fpga: x400: Expand PS GPIO port for DIO control | Javier Valenzuela | 2022-01-25 | 7 | -19/+58 |
* | fpga: x400: Add SPI bus support for GPIO ports | Javier Valenzuela | 2022-01-25 | 9 | -60/+1338 |
* | fpga: x400: Add GPIO control via ATR and DB state | Javier Valenzuela | 2022-01-25 | 14 | -199/+2932 |
* | fpga: x400: Connect Radio Blocks to DIO | Javier Valenzuela | 2022-01-25 | 10 | -305/+626 |
* | fpga: x400: Fix rfnoc_image_core.vh path | Wade Fife | 2022-01-12 | 1 | -1/+1 |
* | fpga: e320: Connect CTRL_IN pins to FPGA | Martin Braun | 2022-01-10 | 2 | -1/+12 |
* | fpga: e320: Remove copy/paste from N310 code | Martin Braun | 2022-01-10 | 1 | -9/+0 |
* | fpga: x300: Fix time register readback | Wade Fife | 2021-12-15 | 1 | -2/+2 |
* | fpga: x300: OR ATR signals going into db_control | Martin Braun | 2021-12-07 | 1 | -1/+10 |
* | fpga: x400: cpld: Add manufacturing support | Humberto Jimenez | 2021-12-01 | 4 | -7/+27 |
* | fpga: x400: Refactor CPLDs build process | Humberto Jimenez | 2021-12-01 | 33 | -254/+733 |
* | x410: correct 100GbE link speed | Andrew Lynch | 2021-11-02 | 2 | -2/+2 |
* | fpga: Shorten line length for Launchpad linter | Aaron Rossetto | 2021-10-28 | 1 | -2/+4 |
* | fpga: x300: Update synchronizer constraint | Wade Fife | 2021-09-13 | 1 | -1/+1 |
* | fpga: n3xx: Update synchronizer constraint | Wade Fife | 2021-09-13 | 1 | -3/+2 |
* | fpga: Remove stale references to UHD_FPGA_DIR | Wade Fife | 2021-09-08 | 1 | -2/+1 |
* | fpga: Set default part for sim in setupenv.sh | Wade Fife | 2021-08-30 | 5 | -0/+20 |
* | x300: Fix sfpp_io_core tuser width | Wade Fife | 2021-08-27 | 1 | -1/+1 |
* | N3xx: Fix White Rabbit | michael-west | 2021-08-04 | 1 | -0/+10 |
* | fpga: x400: Remove stale information in register map | Humberto Jimenez | 2021-07-28 | 3 | -9/+9 |
* | fpga: x400: Fix x4xx_qsfp_wrapper testbench | Wade Fife | 2021-06-22 | 1 | -0/+3 |
* | x400: sim: Move testbenches to sim folder | Wade Fife | 2021-06-17 | 13 | -0/+0 |
* | fpga: Update testbenches to work in ModelSim | Wade Fife | 2021-06-17 | 8 | -89/+232 |
* | fpga: x400: Add makefiles for RF testbenches | Wade Fife | 2021-06-17 | 6 | -0/+209 |
* | fpga: x400: zbx: Add support for ZBX CPLD | Javier Valenzuela | 2021-06-10 | 37 | -0/+17727 |
* | fpga: x400: cpld: Add support for X410 motherboard CPLD | Max Köhler | 2021-06-10 | 42 | -0/+8377 |
* | fpga: x400: Add support for X410 motherboard FPGA | Wade Fife | 2021-06-10 | 204 | -0/+299632 |
* | fpga: Update rfnoc_image_core for all targets | Wade Fife | 2021-06-10 | 18 | -5780/+6492 |
* | fpga: Change RFNoC YAML version numbers to strings | Wade Fife | 2021-06-08 | 10 | -20/+20 |
* | fpga: e320: Improve timing on LVDS interface | Wade Fife | 2020-12-11 | 1 | -3/+2 |
* | fpga: e31x: Add OOT sources to Makefile.e31x.inc | Wade Fife | 2020-11-13 | 1 | -0/+8 |
* | fpga: e31x: Change image file to e310_rfnoc_image_core | Wade Fife | 2020-09-09 | 3 | -5/+5 |
* | E320: Revert addition of Replay block | michael-west | 2020-09-04 | 3 | -266/+270 |
* | fpga: Add Replay Block to RFNoC Core Image | mattprost | 2020-09-03 | 20 | -591/+2586 |
* | fpga: Update DRAM IO signatures | Wade Fife | 2020-09-03 | 4 | -28/+28 |
* | fpga: n3xx: Update AXI interconnect address range | Wade Fife | 2020-08-28 | 4 | -2928/+2217 |
* | fpga: e320: Update AXI interconnect address range | Wade Fife | 2020-08-28 | 2 | -2195/+1373 |
* | fpga: e31x: Change RFNoC Ctrl clock to 40 MHz | Wade Fife | 2020-08-19 | 2 | -1/+3 |
* | fpga: e320: Fix timeout for timekeeper registers | Wade Fife | 2020-08-19 | 1 | -191/+284 |
* | fpga: n3xx: Fix timeout for timekeeper registers | Wade Fife | 2020-08-19 | 3 | -195/+307 |
* | fpga: e31x: Fix timeout for timekeeper registers | Wade Fife | 2020-08-19 | 1 | -180/+278 |
* | fpga: e320: Fix default YAML target to E320_1G | Martin Braun | 2020-08-17 | 1 | -1/+1 |
* | fpga: e310: Fix device in image core YAML | Wade Fife | 2020-08-14 | 1 | -1/+1 |
* | n320: Double radio ingress buffer size | mattprost | 2020-08-12 | 2 | -8/+8 |
* | fpga: n320: Add BIST (AA) image files | steviez | 2020-07-31 | 5 | -0/+1148 |
* | fpga, mpm: Bump FPGA compat number | RobertWalstab | 2020-07-24 | 3 | -3/+3 |