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* fpga: rfnoc: Remove rfnoc_version from target YAMLWade Fife2022-06-101-1/+0
* fpga: Update all RFNoC imagesWade Fife2022-03-312-42/+46
* rfnoc: Update device port names in image core YAMLWade Fife2022-03-311-42/+46
* fpga: Use PROTOVER and CHDR_W from RFNoC image builderWade Fife2022-03-293-6/+25
* fpga: e320: Add DRAM portsWade Fife2022-02-181-97/+97
* fpga: e320: Connect CTRL_IN pins to FPGAMartin Braun2022-01-102-1/+12
* fpga: e320: Remove copy/paste from N310 codeMartin Braun2022-01-101-9/+0
* fpga: Set default part for sim in setupenv.shWade Fife2021-08-301-0/+4
* fpga: Update rfnoc_image_core for all targetsWade Fife2021-06-102-520/+592
* fpga: Change RFNoC YAML version numbers to stringsWade Fife2021-06-081-2/+2
* fpga: e320: Improve timing on LVDS interfaceWade Fife2020-12-111-3/+2
* E320: Revert addition of Replay blockmichael-west2020-09-043-266/+270
* fpga: Add Replay Block to RFNoC Core Imagemattprost2020-09-033-270/+266
* fpga: Update DRAM IO signaturesWade Fife2020-09-031-10/+10
* fpga: e320: Update AXI interconnect address rangeWade Fife2020-08-282-2195/+1373
* fpga: e320: Fix timeout for timekeeper registersWade Fife2020-08-191-191/+284
* fpga: e320: Fix default YAML target to E320_1GMartin Braun2020-08-171-1/+1
* fpga, mpm: Bump FPGA compat numberRobertWalstab2020-07-241-1/+1
* e320: Swap out liberio for internal EthernetAlex Williams2020-07-164-520/+532
* fpga: Update RFNOC_EDGE_TBL_FILE for CygwinWade Fife2020-06-121-1/+1
* Merge FPGA repository back into UHD repositoryMartin Braun2020-01-2867-0/+54529