| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | fpga: e31x: Fix DRAM traffic gen IP name | Wade Fife | 2022-03-23 | 1 | -1/+1 |
| | | | | | | Change name in DRAM IP Makefile from IP_MIG_7SERIES_TG_SRCS to IP_DDR3_16BIT_TG_SRCS to match the naming of other variables. | ||||
| * | fpga: e31x: Add DRAM support | Wade Fife | 2022-02-10 | 4 | -0/+2961 |
| This adds DRAM support to E31x devices. Due to the size of the DDR3 memory controller, it is not enabled by default. You can include the memory controller IP in the build by adding the DRAM environment variable to your build. For example: DRAM=1 make E310_SG3 | |||||
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