uhd - Ettus' UHD Repository

	Commit message (Expand)	Author	Age	Files	Lines
*	fpga: tools: Fix adding directories for HDL source	Wade Fife	2022-01-13	1	-1/+1
*	fpga: hls: Add version to generated HLS IP	Wade Fife	2022-01-13	1	-2/+2
*	fpga: tools: Update Vivado scripts to use python3	Wade Fife	2021-12-08	1	-4/+4
*	fpga: Update help message for setupenv.sh	Wade Fife	2021-09-10	1	-5/+7
*	fpga: tools: Add UHD_FPGA_DIR definition to synthesis	Wade Fife	2021-09-08	1	-2/+6
*	fpga: Fix Xilinx bitfile parser for Python 3	Martin Braun	2021-08-24	1	-31/+54
*	fpga: tools: Detect assertions in ModelSim simulation	Wade Fife	2021-06-17	1	-2/+22
*	fpga: tools: Put SIM_SRCS at end of compile order	Wade Fife	2021-06-17	1	-1/+1
*	fpga: tools: Add modelsim.ini to ModelSim calls	Wade Fife	2021-06-17	3	-7/+36
*	fpga: tools: Fix part selection in setupenv	Sam O'Brien	2021-06-10	1	-4/+12
*	fpga: tools: Add ability to run commands before route	Wade Fife	2021-06-03	1	-5/+11
*	fpga: tools: Add ability to patch IP during generation	Wade Fife	2021-06-03	1	-0/+54
*	fpga: tools: Add support for RFSoC	Humberto Jimenez	2021-06-03	2	-9/+9
*	fpga: Remove Python2 support from build system	Martin Braun	2021-01-04	6	-43/+40
*	fpga: tools: Highlight suppressible errors from vlint	Wade Fife	2020-06-29	1	-1/+1
*	fpga: tools: Fix ModelSim return status	Wade Fife	2020-06-18	2	-5/+12
*	fpga: tools: Improve detection of setupenv sourcing	Wade Fife	2020-05-28	1	-29/+31
*	fpga: tools: Improve native ModelSim support	Wade Fife	2020-05-26	2	-0/+217
*	fpga: tools: Add contents of directories for HDL source	Wade Fife	2020-05-26	2	-4/+25
*	fpga: tools: Remove uhd_image_builder	Martin Braun	2020-05-18	4	-1244/+0
*	fpga: tools: Fix HLS IP build with Cygwin	Humberto Jimenez	2020-05-12	1	-1/+6
*	fpga: tools: Option to check for full Vivado version	Humberto Jimenez	2020-04-14	1	-0/+24
*	fpga: tools: Add support for .sdc in Vivado	Paul Butler	2020-04-02	1	-0/+3
*	fpga: tools: Add default Vivado install location	Wade Fife	2020-04-01	1	-1/+5
*	fpga: tools: Add modelsim to make sim targets	Andrew Moch	2020-03-20	1	-14/+18
*	fpga: tools: Ignore BD layout info for TCL-based BD	Humberto Jimenez	2020-03-12	1	-1/+1
*	Merge FPGA repository back into UHD repository	Martin Braun	2020-01-28	25	-0/+3817