| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | fpga: Update testbenches to work in ModelSim | Wade Fife | 2021-06-17 | 3 | -47/+71 |
| * | fpga: lib: Update register comments in eth_regs.vh | Wade Fife | 2021-06-10 | 1 | -1/+5 |
| * | fpga: lib: Add modports to SV AXI-Stream blocks | Wade Fife | 2021-06-03 | 4 | -8/+8 |
| * | fpga: lib: Add time_increment port to timekeeper | Wade Fife | 2021-06-03 | 1 | -17/+43 |
| * | fpga: lib: Pipeline ctrlport_timer | Wade Fife | 2021-06-03 | 1 | -24/+81 |
| * | fpga: lib: Add clock domain comments to interfaces | Wade Fife | 2021-06-03 | 7 | -13/+28 |
| * | fpga: lib: Add 2 to 1 gearbox module | Wade Fife | 2021-06-03 | 5 | -0/+517 |
| * | fpga: lib: Add AXI4 (full) interface | Andrew Moch | 2021-06-03 | 4 | -0/+619 |
| * | fpga: lib: add pause support to ethernet xport | Andrew Moch | 2021-06-03 | 6 | -7/+112 |
| * | fpga: lib: Add eth_ipv4_internal | Wade Fife | 2021-06-03 | 2 | -0/+442 |
| * | fpga: lib: Add zynquplus family to axi_bitq | Humberto Jimenez | 2021-06-03 | 1 | -12/+13 |
| * | fpga: lib: Minor cleanup of axi_lite.vh | Lars Amsel | 2021-06-03 | 1 | -2/+23 |
| * | fpga: rfnoc: Add ability to disable output flow control | Wade Fife | 2021-04-14 | 2 | -7/+22 |
| * | fpga: lib: Add rx_front_end_gen3 testbench | Wade Fife | 2021-04-09 | 2 | -0/+247 |
| * | fpga: lib: Update round_sd to eliminate X from simulation | Wade Fife | 2021-04-09 | 1 | -14/+45 |
| * | fpga: lib: Fix simulation of axi_fir_filter | Wade Fife | 2021-04-09 | 1 | -1/+1 |
| * | TwinRX: Remove frontend filter | michael-west | 2021-04-08 | 1 | -59/+8 |
| * | fpga: docs: Improve documentation of rx_frontend_gen3 | Martin Braun | 2021-04-07 | 1 | -1/+73 |
| * | fpga: lib: Fix DDS_SIN_COS_LUT outputs in makefile | Paul Butler | 2021-03-31 | 1 | -1/+1 |
| * | fpga: dsp: Fix formatting of rx_dcoffset and add docs | Martin Braun | 2021-03-09 | 1 | -38/+110 |
| * | fpga: e320: Improve timing on LVDS interface | Wade Fife | 2020-12-11 | 3 | -355/+539 |
| * | fpga: lib: add glitch free mux module | Max Köhler | 2020-12-03 | 2 | -0/+30 |
| * | fpga: lib: Fix axis_strm_monitor parameters | Wade Fife | 2020-10-20 | 1 | -2/+2 |
| * | fpga: lib: Fix small packets stuck in 10 GbE TX | Andrew Moch | 2020-10-05 | 1 | -3/+17 |
| * | fpga: lib: Fix 10 GbE cut-through mode | Andrew Moch | 2020-09-16 | 1 | -4/+16 |
| * | fpga: lib: add generic to disable bitq engine tri-stating | Max Köhler | 2020-09-16 | 2 | -11/+16 |
| * | fpga: sim: chdr_stream_endpoint_tb improvements | Wade Fife | 2020-08-31 | 2 | -36/+150 |
| * | fpga: rfnoc: Update CHDR stream INIT command | Wade Fife | 2020-08-28 | 1 | -3/+10 |
| * | fpga: lib: Fix lint warnings | Wade Fife | 2020-08-28 | 3 | -3/+3 |
| * | fpga: rfnoc: Remove deprecated files | Wade Fife | 2020-08-23 | 22 | -2674/+5 |
| * | fpga: lib: Add more CtrlPort constants | Wade Fife | 2020-08-19 | 1 | -7/+12 |
| * | fpga: lib: Add ctrlport_to_regport bridge | Wade Fife | 2020-08-19 | 2 | -0/+91 |
| * | fpga: rfnoc: Enable clean switch in Switchboard | Wade Fife | 2020-08-13 | 1 | -1/+1 |
| * | fpga: lib: Fix SWITCH_ON_LAST in axi_mux_select | Wade Fife | 2020-08-13 | 1 | -18/+39 |
| * | fpga: lib: add handshake to replace FIFO for ctrlport CDC | Max Köhler | 2020-08-13 | 3 | -48/+143 |
| * | fpga: rfnoc: Fix clock crossing in axis_data_to_chdr | Wade Fife | 2020-08-12 | 1 | -69/+89 |
| * | fpga: lib: Change max FFT size to 1024 | Wade Fife | 2020-08-11 | 1 | -2/+2 |
| * | fpga: rfnoc: Add tests to FFT block | Wade Fife | 2020-08-10 | 2 | -39/+202 |
| * | fpga: lib: add Intel MAX10 architecture for 2clk FIFO | Max Köhler | 2020-08-06 | 2 | -28/+33 |
| * | fpga: lib: Update xport_sv | Andrew Moch | 2020-08-05 | 6 | -182/+437 |
| * | fpga: rfnoc: Add RFNoC Keep One in N block | Aaron Rossetto | 2020-08-05 | 7 | -0/+1432 |
| * | fpga: rfnoc: Add RFNoC Replay block | Wade Fife | 2020-08-04 | 11 | -875/+4101 |
| * | fpga: rfnoc: Add 4 KiB boundary check to sim_axi_ram | Wade Fife | 2020-08-04 | 1 | -0/+12 |
| * | fpga: rfnoc: Add support for CHDR_W < ITEM_W*NIPC | Wade Fife | 2020-08-04 | 2 | -137/+195 |
| * | fpga: lib: Fix comments and indentation in axi_fifo_short.v | Wade Fife | 2020-08-04 | 1 | -98/+87 |
| * | fpga: lib: Add xge features for new xport_sv | Andrew Moch | 2020-07-31 | 1 | -100/+191 |
| * | fpga: lib: Update AxiLiteIf | Andrew Moch | 2020-07-31 | 1 | -1/+74 |
| * | fpga: lib: Fix chdr_mgmt_pkt_handler when CHDR_W != 64 | Andrew Moch | 2020-07-30 | 1 | -1/+1 |
| * | fpga: rfnoc: Add Signal Generator RFNoC block | Wade Fife | 2020-07-30 | 12 | -18/+1925 |
| * | fpga: lib: Add axis_packetize module | Wade Fife | 2020-07-30 | 2 | -0/+162 |
