uhd - Ettus' UHD Repository

	Commit message (Expand)	Author	Age	Files	Lines
*	fpga: lib: Update register comments in eth_regs.vh	Wade Fife	2021-06-10	1	-1/+5
*	fpga: lib: Add time_increment port to timekeeper	Wade Fife	2021-06-03	1	-17/+43
*	fpga: lib: Pipeline ctrlport_timer	Wade Fife	2021-06-03	1	-24/+81
*	fpga: lib: Add clock domain comments to interfaces	Wade Fife	2021-06-03	5	-11/+24
*	fpga: lib: add pause support to ethernet xport	Andrew Moch	2021-06-03	5	-6/+111
*	fpga: lib: Add eth_ipv4_internal	Wade Fife	2021-06-03	2	-0/+442
*	fpga: rfnoc: Add ability to disable output flow control	Wade Fife	2021-04-14	2	-7/+22
*	fpga: lib: Add rx_front_end_gen3 testbench	Wade Fife	2021-04-09	2	-0/+247
*	fpga: lib: Fix simulation of axi_fir_filter	Wade Fife	2021-04-09	1	-1/+1
*	TwinRX: Remove frontend filter	michael-west	2021-04-08	1	-59/+8
*	fpga: docs: Improve documentation of rx_frontend_gen3	Martin Braun	2021-04-07	1	-1/+73
*	fpga: sim: chdr_stream_endpoint_tb improvements	Wade Fife	2020-08-31	2	-36/+150
*	fpga: rfnoc: Update CHDR stream INIT command	Wade Fife	2020-08-28	1	-3/+10
*	fpga: lib: Fix lint warnings	Wade Fife	2020-08-28	3	-3/+3
*	fpga: rfnoc: Remove deprecated files	Wade Fife	2020-08-23	13	-2016/+1
*	fpga: lib: Add more CtrlPort constants	Wade Fife	2020-08-19	1	-7/+12
*	fpga: rfnoc: Enable clean switch in Switchboard	Wade Fife	2020-08-13	1	-1/+1
*	fpga: lib: add handshake to replace FIFO for ctrlport CDC	Max Köhler	2020-08-13	1	-48/+60
*	fpga: rfnoc: Fix clock crossing in axis_data_to_chdr	Wade Fife	2020-08-12	1	-69/+89
*	fpga: rfnoc: Add tests to FFT block	Wade Fife	2020-08-10	2	-39/+202
*	fpga: lib: add Intel MAX10 architecture for 2clk FIFO	Max Köhler	2020-08-06	1	-20/+25
*	fpga: lib: Update xport_sv	Andrew Moch	2020-08-05	6	-182/+437
*	fpga: rfnoc: Add RFNoC Keep One in N block	Aaron Rossetto	2020-08-05	7	-0/+1432
*	fpga: rfnoc: Add RFNoC Replay block	Wade Fife	2020-08-04	9	-7/+4101
*	fpga: rfnoc: Add 4 KiB boundary check to sim_axi_ram	Wade Fife	2020-08-04	1	-0/+12
*	fpga: rfnoc: Add support for CHDR_W < ITEM_W*NIPC	Wade Fife	2020-08-04	2	-137/+195
*	fpga: lib: Fix chdr_mgmt_pkt_handler when CHDR_W != 64	Andrew Moch	2020-07-30	1	-1/+1
*	fpga: rfnoc: Add Signal Generator RFNoC block	Wade Fife	2020-07-30	10	-0/+1903
*	fpga: Add Switchboard RFNoC block	Jesse Zhang	2020-07-30	7	-0/+1121
*	TwinRX: Fix increased noise floor	michael-west	2020-07-21	1	-1/+1
*	fpga: remove liberio	RobertWalstab	2020-07-20	3	-126/+2
*	fpga: rfnoc: Fix testbenches to run under ModelSim	Wade Fife	2020-07-20	7	-84/+61
*	fpga: rfnoc: Add RFNoC Moving Average block	Wade Fife	2020-07-16	8	-0/+1587
*	fpga: lib: modify ctrlport decoder to Verilog 2001 compatible syntax	Max Köhler	2020-07-10	1	-39/+41
*	fpga: lib: Add width agnostic version of Ethernet Interface	Andrew Moch	2020-06-30	13	-0/+3339
*	fpga: rfnoc: Add Log-Power block	Wade Fife	2020-06-29	6	-0/+1006
*	fpga: rfnoc: Fix chdr_update_length function	Wade Fife	2020-06-29	1	-1/+1
*	fpga: rfnoc: Add RFNoC Window block	Wade Fife	2020-06-29	8	-0/+1454
*	fpga: rfnoc: Fix read suppression test in rfnoc_block_axi_ram_fifo_tb	Wade Fife	2020-06-25	1	-8/+16
*	fpga: lib: Pipeline and add clken to ip_hdr_checksum	Andrew Moch	2020-06-24	1	-2/+2
*	fpga: rfnoc: Add support for 512-bit CHDR widths	Andrew Moch	2020-06-18	16	-220/+358
*	fpga: rfnoc: Add defaults for rate changing	Wade Fife	2020-05-28	2	-10/+14
*	fpga: rfnoc: Add RFNoC Add/Sub block	Wade Fife	2020-05-28	6	-0/+1183
*	rfnoc: Add Split Stream RFNoC block	Wade Fife	2020-05-28	6	-0/+932
*	fpga: rfnoc: Add Vector IIR RFNoC block	Wade Fife	2020-05-19	7	-17/+1393
*	fpga: rfnoc: Clean up ctrlport_splitter usage	Wade Fife	2020-05-12	2	-2/+2
*	fpga: utils: Optimize ctrlport_splitter for NUM_SLAVES = 1	Wade Fife	2020-05-12	1	-45/+61
*	TwinRX: Remove decimation from frontend	Michael West	2020-05-12	1	-36/+52
*	DUC/DDC: Add variable time increment	Michael West	2020-05-12	5	-19/+39
*	fpga: Change default MTU to 10	Wade Fife	2020-05-11	5	-5/+5