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* fpga: Fix first arg in calls to $fatal()Wade Fife2022-07-201-11/+11
| | | | | | This fixes warnings regarding the first argument to $fatal(), which is supposed to be a number indicating what diagnostics to display. 1 corresponds to "Prints simulation time and location".
* rfnoc: Fix test_timed_commands for RFNoC devicesmichael-west2022-04-051-16/+62
| | | | | | | - Added command time to readback of time from Radio block. - Added wait for time to readback of shared registers in Radio block. Signed-off-by: michael-west <michael.west@ettus.com>
* FPGA: Replay block version 1.1michael-west2022-04-013-50/+266
| | | | | | | | | | | | | | | - Add registers to read current record and play positions. - Add register to read current space in play command FIFO to allow software to avoid overflowing the FIFO. - Cache base address and size with play command in command FIFO. - Fix timestamp logic. Timestamp is only for the first packet of a burst. The increment of 1 for each sample is not accurate because it assumed the Replay block was playing at the same rate as the Radio, which cannot be assumed. Maintained backwards compatibility with older API. Signed-off-by: michael-west <michael.west@ettus.com>
* fpga: rfnoc: Fix PPS edge detectionmichael-west2022-03-091-1/+1
| | | | | | | Make timekeeper module sample rising edge instead of falling edge of PPS signal. Signed-off-by: michael-west <michael.west@ettus.com>
* fpga: rfnoc: Make Replay packet length independent of burst sizeWade Fife2022-03-092-106/+158
| | | | | | | | | | | | | Before this change, the packet size output by the Replay block during playback was limited to length of a full memory burst transaction. This led to relatively small packets during playback (typically 2 KiB) and had other side effects, such as simultaneous playback from two different memory locations using different packet sizes because of differences in memory alignment. With this change, the configured packet size, as set by the register REG_PLAY_WORDS_PER_PKT, is used for all packets except the last packet of playback, which can of course be smaller.
* fgpa: rfnoc: Set Replay memory transactions to 2 KiBWade Fife2022-03-092-7/+15
| | | | | | | This sets the Replay block's counter width so that memory bursts are up to 2 KiB. Previously, the counter width was fixed, which meant that wide memories would require especially large buffers and could exceed the 4 KiB limit imposed by AXI.
* fpga: rfnoc: Fix strobe probability in radio simulatorWade Fife2022-03-041-7/+7
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* fpga: rfnoc: Regenerate noc_shellsWade Fife2022-03-0418-29/+47
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* fpga: rfnoc: Change AWIDTH default for axi_ram_fifoWade Fife2022-02-101-1/+1
| | | | | Change AWIDTH to be the same as MEM_ADDR_W by default. Current USRPs assume the AXI address width is the same as MEM_ADDR_W.
* fpga: rfnoc: Add BLANK_OUTPUT to FIR filter block's parametersJonathon Pendlum2022-02-103-11/+20
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* fpga: Remove noc_shell_regs.vh and sim_rfnoc_lib.svhMartin Braun2022-01-252-26/+0
| | | | | Both files are a UHD 3 remnant and potentially confusing for UHD 4 codebase readers.
* fpga: x400: Connect Radio Blocks to DIOJavier Valenzuela2022-01-252-0/+74
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* rfnoc: Fix noc_shell direction commentsWade Fife2021-12-0818-81/+86
| | | | | | Some comments describing data flow direction were wrong. This commit updates the Mako files and updates the noc_shell modules with newly generated versions.
* fpga: Add ability to get time from Radio blockmichael-west2021-11-173-2/+26
| | | | | | Added registers to read back radio time. Bumped minor compat. Signed-off-by: michael-west <michael.west@ettus.com>
* fpga: rfnoc: Add RFNoC CHDR resize moduleWade Fife2021-11-047-0/+2031
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* fpga: rfnoc: Add CHDR management util functionsWade Fife2021-11-041-4/+85
| | | | Add missing chdr_mgmt_*() and enum_to_chdr_w() functions.
* fpga: rfnoc: Add labels to axi_switch generate blocksWade Fife2021-10-281-36/+67
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* fpga: rfnoc: Add labels to chdr_mgmt_pkt_handlerWade Fife2021-10-281-30/+45
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* fpga: rfnoc: Add documentation to chdr_xb_routing_tableWade Fife2021-10-281-46/+84
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* siggen: Fix direction of rotationWade Fife2021-10-274-35/+44
| | | | | | | | | The I and Q were swapped in sine_tone, which caused confusion and made the rotation of REG_CARTESIAN clockwise by default. This effectively made the resulting frequency negative. This PR makes the I and Q order consistent with RFNoC and fixes the direction of rotation so that a positive value for REG_PHASE_INC (phase increment) results in a counter-clockwise rotation, which yields a positive frequency.
* fpga: Remove stale references to UHD_FPGA_DIRWade Fife2021-09-087-14/+7
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* fpga: rfnoc: Fix EOB loss in DUCWade Fife2021-08-086-212/+1850
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | There were some rare corner cases where the EOB could get lost in the DUC due to the dds_timed logic not always passing it through as it should. This resulted in an underflow error message at the end of transmission. This commit also fixes an issue where part of the last packet used a frequency shift of 0 instead of the requested frequency shift, and an issue where the first few samples of a burst used the wrong frequency shift value. Part of the fix includes adding a TUSER port to dds_sin_cos_lut_only. The TUSER port is built into the IP but was disabled. It is now enabled and set to 1 bit wide. This has a very small effect on resource usage and can be left unconnected when not needed. The dds_freq_tune block was shared by the DUC and DDC. To avoid affecting the DDC, a new version, dds_freq_tune_duc, is being added for the DUC to use that has the necessary fixes. The new dds_wrapper.v is a wrapper for the dds_sin_cos_lut_only IP. This IP has the undesirable behavior that new inputs must be provided to push previous outputs through the IP. This wrapper hides that complexity by adding some logic to ensure all data gets pushed through automatically. This logic uses the TUSER port on the IP. Finally, a testbench for dds_timed was added.
* fpga: lib: Clean up and document lib filesWade Fife2021-08-083-246/+411
| | | | Clean-up and document axi_tag_time, dds_freq_tune, and axi_sync.
* rfnoc: duc: Remove stale references to CORDICWade Fife2021-08-081-18/+15
| | | | | Updated some comments that still referenced the old CORDIC implementation, which is no longer used.
* fpga: Update testbenches to work in ModelSimWade Fife2021-06-172-36/+55
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* fpga: lib: Update register comments in eth_regs.vhWade Fife2021-06-101-1/+5
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* fpga: lib: Add time_increment port to timekeeperWade Fife2021-06-031-17/+43
| | | | | Adds a time_increment port for situations in which the parameter TIME_INCREMENT can't be used. They offer the same behavior.
* fpga: lib: Pipeline ctrlport_timerWade Fife2021-06-031-24/+81
| | | | | | | This pipelines ctrlport_timer to eliminate the long combinational path caused by the time comparisons. This change also removes the PRECISION_BITS parameter and converts it to a signal named time_ignore_bits.
* fpga: lib: Add clock domain comments to interfacesWade Fife2021-06-035-11/+24
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* fpga: lib: add pause support to ethernet xportAndrew Moch2021-06-035-6/+111
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* fpga: lib: Add eth_ipv4_internalWade Fife2021-06-032-0/+442
| | | | | This adds a generic version of eth_internal that allows you to specify the CHDR width.
* fpga: rfnoc: Add ability to disable output flow controlWade Fife2021-04-142-7/+22
| | | | | | | | | | | | | Per the RFNoC specification, if we set the frequency of flow control updates to 0 then the input stream will not send flow control status updates to the output stream handler. This change makes it so that when the frequency of flow control status updates is configured to be zero in the FPGA output stream handler (i.e., cfg_fc_freq_bytes and cfg_fc_freq_pkts are both 0 in chdr_stream_output) then the output stream handler will not use flow control. That is, chdr_stream_output will not expect stream status updates and will not restrict output packets.
* fpga: lib: Add rx_front_end_gen3 testbenchWade Fife2021-04-092-0/+247
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* fpga: lib: Fix simulation of axi_fir_filterWade Fife2021-04-091-1/+1
| | | | | | The always(*) block was never executing in some simulators because there were no signals on the right-hand side in the block. Changing it to an initial block ensures it always runs.
* TwinRX: Remove frontend filtermichael-west2021-04-081-59/+8
| | | | | | | | | | Removing the FIR filter in the frontend to reclaim resources and remove redundancy when using a DDC block. The default image has a DDC block, so only users making custom RFNoC images and using TwinRX will need to take care to properly downconvert the full bandwidth coming from the radio block. Signed-off-by: michael-west <michael.west@ettus.com>
* fpga: docs: Improve documentation of rx_frontend_gen3Martin Braun2021-04-071-1/+73
| | | | Also fixes a typo in the calibration manual page.
* fpga: sim: chdr_stream_endpoint_tb improvementsWade Fife2020-08-312-36/+150
| | | | | | | - Adds test coverage for stream command and status packets - Cleans up report output during simulation - Stops clocks at the end of simulation, so chdr_stream_endpoint_tb can be run directly instead of just chdr_stream_endpoint_all_tb
* fpga: rfnoc: Update CHDR stream INIT commandWade Fife2020-08-281-3/+10
| | | | | | This changes the behavior of the stream command with the INIT OpCode such that sending the command with 0 for the values causes no flow control stream status packets to be sent in response to incoming data.
* fpga: lib: Fix lint warningsWade Fife2020-08-283-3/+3
| | | | | Fixes various synthesis/simulation warnings that were being generated due to incorrectly sized constants.
* fpga: rfnoc: Remove deprecated filesWade Fife2020-08-2313-2016/+1
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* fpga: lib: Add more CtrlPort constantsWade Fife2020-08-191-7/+12
| | | | Add some missing CtrlPort signal widths to ctrlport.vh.
* fpga: rfnoc: Enable clean switch in SwitchboardWade Fife2020-08-131-1/+1
| | | | | This change prevents packets from being chopped midway if the switchboard configuration is changed when a packet is in flight.
* fpga: lib: add handshake to replace FIFO for ctrlport CDCMax Köhler2020-08-131-48/+60
| | | | | | | | The clock crossing of the ctrlport used FIFOs to transfer requests and responses between clock domains. This commit adds a handshake based on the pulse synchronizer to reduce the resource usage for ctrlport clock domain crossing. Data is stored in a single register while the pulse synchronizer handles the signaling of valid flags.
* fpga: rfnoc: Fix clock crossing in axis_data_to_chdrWade Fife2020-08-121-69/+89
| | | | | | | | | This fixes some incorrectly handled clock crossings from axis_data_clk to axis_chdr_clk, which could have manifested as timing failures (on E320) or incorrect behavior, depending on the product and noc_shell configuration. Also cleans up trailing white space.
* fpga: rfnoc: Add tests to FFT blockWade Fife2020-08-102-39/+202
| | | | | This adds additional tests to the testbench to cover register reads and basic IFFT functionaltiy.
* fpga: lib: add Intel MAX10 architecture for 2clk FIFOMax Köhler2020-08-061-20/+25
| | | | | | | | | | | | | This commit derives parameters for MAX10 devices if provided by the DEVICE parameter. MAX10 devices FIFO generator support up to 36 bit wide FIFOs using embedded memory (M9K) in simple dual port mode, which is treated equally to RAM in the parameters. In combination with sorting the ctrlport signals by usage, the used resources can be reduced on the MAX10 devices from 6 to 3 M9K blocks for a ctrlport_clk_cross instance without time and portids.
* fpga: lib: Update xport_svAndrew Moch2020-08-056-182/+437
| | | | | | | | | - Detect dropped words at the dispatch level. This prevents an overflow on CHDR from block CPU. - Dropped packets are recorded as CPU or CHDR drop count - Refactor to put chdr_xport_adapter.sv in different clock domain to improve timing - Unwrinkle tkeep/trailing transitions
* fpga: rfnoc: Add RFNoC Keep One in N blockAaron Rossetto2020-08-057-0/+1432
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* fpga: rfnoc: Add RFNoC Replay blockWade Fife2020-08-049-7/+4101
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* fpga: rfnoc: Add 4 KiB boundary check to sim_axi_ramWade Fife2020-08-041-0/+12
| | | | | Adding a check for bursts that cross the 4 KiB boundary to the AXI4 memory model. Crossing a 4 KiB boundary is not allowed by AXI4.
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