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path: root/fpga/usrp3/lib/rfnoc
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* fpga: Fix first arg in calls to $fatal()Wade Fife2022-07-201-11/+11
* rfnoc: Fix test_timed_commands for RFNoC devicesmichael-west2022-04-051-16/+62
* FPGA: Replay block version 1.1michael-west2022-04-013-50/+266
* fpga: rfnoc: Fix PPS edge detectionmichael-west2022-03-091-1/+1
* fpga: rfnoc: Make Replay packet length independent of burst sizeWade Fife2022-03-092-106/+158
* fgpa: rfnoc: Set Replay memory transactions to 2 KiBWade Fife2022-03-092-7/+15
* fpga: rfnoc: Fix strobe probability in radio simulatorWade Fife2022-03-041-7/+7
* fpga: rfnoc: Regenerate noc_shellsWade Fife2022-03-0418-29/+47
* fpga: rfnoc: Change AWIDTH default for axi_ram_fifoWade Fife2022-02-101-1/+1
* fpga: rfnoc: Add BLANK_OUTPUT to FIR filter block's parametersJonathon Pendlum2022-02-103-11/+20
* fpga: Remove noc_shell_regs.vh and sim_rfnoc_lib.svhMartin Braun2022-01-252-26/+0
* fpga: x400: Connect Radio Blocks to DIOJavier Valenzuela2022-01-252-0/+74
* rfnoc: Fix noc_shell direction commentsWade Fife2021-12-0818-81/+86
* fpga: Add ability to get time from Radio blockmichael-west2021-11-173-2/+26
* fpga: rfnoc: Add RFNoC CHDR resize moduleWade Fife2021-11-047-0/+2031
* fpga: rfnoc: Add CHDR management util functionsWade Fife2021-11-041-4/+85
* fpga: rfnoc: Add labels to axi_switch generate blocksWade Fife2021-10-281-36/+67
* fpga: rfnoc: Add labels to chdr_mgmt_pkt_handlerWade Fife2021-10-281-30/+45
* fpga: rfnoc: Add documentation to chdr_xb_routing_tableWade Fife2021-10-281-46/+84
* siggen: Fix direction of rotationWade Fife2021-10-274-35/+44
* fpga: Remove stale references to UHD_FPGA_DIRWade Fife2021-09-087-14/+7
* fpga: rfnoc: Fix EOB loss in DUCWade Fife2021-08-086-212/+1850
* fpga: lib: Clean up and document lib filesWade Fife2021-08-083-246/+411
* rfnoc: duc: Remove stale references to CORDICWade Fife2021-08-081-18/+15
* fpga: Update testbenches to work in ModelSimWade Fife2021-06-172-36/+55
* fpga: lib: Update register comments in eth_regs.vhWade Fife2021-06-101-1/+5
* fpga: lib: Add time_increment port to timekeeperWade Fife2021-06-031-17/+43
* fpga: lib: Pipeline ctrlport_timerWade Fife2021-06-031-24/+81
* fpga: lib: Add clock domain comments to interfacesWade Fife2021-06-035-11/+24
* fpga: lib: add pause support to ethernet xportAndrew Moch2021-06-035-6/+111
* fpga: lib: Add eth_ipv4_internalWade Fife2021-06-032-0/+442
* fpga: rfnoc: Add ability to disable output flow controlWade Fife2021-04-142-7/+22
* fpga: lib: Add rx_front_end_gen3 testbenchWade Fife2021-04-092-0/+247
* fpga: lib: Fix simulation of axi_fir_filterWade Fife2021-04-091-1/+1
* TwinRX: Remove frontend filtermichael-west2021-04-081-59/+8
* fpga: docs: Improve documentation of rx_frontend_gen3Martin Braun2021-04-071-1/+73
* fpga: sim: chdr_stream_endpoint_tb improvementsWade Fife2020-08-312-36/+150
* fpga: rfnoc: Update CHDR stream INIT commandWade Fife2020-08-281-3/+10
* fpga: lib: Fix lint warningsWade Fife2020-08-283-3/+3
* fpga: rfnoc: Remove deprecated filesWade Fife2020-08-2313-2016/+1
* fpga: lib: Add more CtrlPort constantsWade Fife2020-08-191-7/+12
* fpga: rfnoc: Enable clean switch in SwitchboardWade Fife2020-08-131-1/+1
* fpga: lib: add handshake to replace FIFO for ctrlport CDCMax Köhler2020-08-131-48/+60
* fpga: rfnoc: Fix clock crossing in axis_data_to_chdrWade Fife2020-08-121-69/+89
* fpga: rfnoc: Add tests to FFT blockWade Fife2020-08-102-39/+202
* fpga: lib: add Intel MAX10 architecture for 2clk FIFOMax Köhler2020-08-061-20/+25
* fpga: lib: Update xport_svAndrew Moch2020-08-056-182/+437
* fpga: rfnoc: Add RFNoC Keep One in N blockAaron Rossetto2020-08-057-0/+1432
* fpga: rfnoc: Add RFNoC Replay blockWade Fife2020-08-049-7/+4101
* fpga: rfnoc: Add 4 KiB boundary check to sim_axi_ramWade Fife2020-08-041-0/+12
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