uhd - Ettus' UHD Repository

	Commit message (Expand)	Author	Age	Files	Lines
*	fpga: rfnoc: Add gate to dynamically enable control-port interfaces	Max Köhler	2020-04-01	1	-0/+91
*	fpga: rfnoc: ctrport_combiner with deterministic latency for PRIORITY=1	Max Köhler	2020-04-01	1	-13/+51
*	fpga: Fix errors found by linting with vsim	Andrew Moch	2020-03-23	2	-3/+6
*	sim: Add item support to RFNoC simulation	Wade Fife	2020-03-09	6	-6/+6
*	sim: Parameterize chdr_word_t data type	Wade Fife	2020-03-09	8	-8/+30
*	fpga: lib: Modify for loop to Verilog 2001 syntax	Max Köhler	2020-03-09	1	-34/+35
*	rfnoc: Fix FIR and AXI RAM block register documentation	Wade Fife	2020-03-05	2	-9/+11
*	rfnoc: Add management filter to generic xport	Wade Fife	2020-02-19	3	-71/+138
*	radio: Update TB to use new block ctrl connect	Wade Fife	2020-02-19	1	-41/+17
*	rfnoc: Update blocks to use autogenerated noc_shell	Wade Fife	2020-02-06	23	-1825/+2407
*	Merge FPGA repository back into UHD repository	Martin Braun	2020-01-28	246	-0/+47221