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* fpga: Update testbenches to work in ModelSimWade Fife2021-06-172-36/+55
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* fpga: lib: Update register comments in eth_regs.vhWade Fife2021-06-101-1/+5
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* fpga: lib: Add clock domain comments to interfacesWade Fife2021-06-035-11/+24
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* fpga: lib: add pause support to ethernet xportAndrew Moch2021-06-035-6/+111
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* fpga: lib: Add eth_ipv4_internalWade Fife2021-06-032-0/+442
| | | | | This adds a generic version of eth_internal that allows you to specify the CHDR width.
* fpga: lib: Update xport_svAndrew Moch2020-08-056-182/+437
| | | | | | | | | - Detect dropped words at the dispatch level. This prevents an overflow on CHDR from block CPU. - Dropped packets are recorded as CPU or CHDR drop count - Refactor to put chdr_xport_adapter.sv in different clock domain to improve timing - Unwrinkle tkeep/trailing transitions
* fpga: rfnoc: Fix testbenches to run under ModelSimWade Fife2020-07-201-11/+10
| | | | | | This updates the makefiles for the testbenches so they can be run using "make modelsim" without any additional hacks. The "xsim" and "vsim" simulation targets also still work.
* fpga: lib: Add width agnostic version of Ethernet InterfaceAndrew Moch2020-06-3013-0/+3339
The rnfoc/xport section is refactored in System Verilog to allow the following improvements (1) CPU_W - Sets the size of the c2e and e2c pipes. This can be run at a different clock rate than the main ethernet pipe (2) CHDR_W - Sets the size of the v2e and e2v pipes. This can be run at a different clock rate than the main ethernet pipe (3) ENET_W - Sets the size of the eth_tx and eth_rx pipes. eth_interface_tb runs traffic from e2c,e2v,v2e,c2e simultaneously against the original xport_sv implementation, and against the new implementation with widths of 64/128/512. A chdr_management node info request queries the port info of the node0 in the eth_interface. eth_ifc_synth_test.sv can be compiled with the make xsim target to test out the size of various configurations.