uhd - Ettus' UHD Repository

	Commit message (Collapse)	Author	Age	Files	Lines
*	fpga: lib: Add modports to SV AXI-Stream blocks	Wade Fife	2021-06-03	4	-8/+8
\|
*	fpga: lib: Add clock domain comments to interfaces	Wade Fife	2021-06-03	1	-0/+1
\|
*	fpga: lib: add pause support to ethernet xport	Andrew Moch	2021-06-03	1	-1/+1
\|
*	fpga: lib: Add synthesizable AXI4-Stream SV components	Andrew Moch	2020-06-25	15	-0/+3201
	Components are connected together with AxiStreamIfc. Some features include: (1) Add bytes to the start of a packet (2) Remove bytes from a packet (3) Wrappers for some older components a. fifo - buffer but imediately pass a packet b. packet_gate - buffer and hold till end of packet c. width_conv - cross clock domains and change width of axi bus The AxiStreamIf was moved from PkgAxiStreamBfm to its own file. It can be used to connect to ports with continuous assignment. AxiStreamPacketIf must be used procedurally but allows the following new methods: - reached_packet_byte - notify when tdata contains a paritcular byte - get_packet_byte/get_packet_field - extract a byte or field from axi - put_packet_byte/put_packet_field - overwrite a byte or field onto axi