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path: root/fpga/usrp3/lib/axi4s_sv/axi4s_fifo.sv
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* fpga: lib: Add modports to SV AXI-Stream blocksWade Fife2021-06-031-2/+2
* fpga: lib: Add clock domain comments to interfacesWade Fife2021-06-031-0/+1
* fpga: lib: add pause support to ethernet xportAndrew Moch2021-06-031-1/+1
* fpga: lib: Add synthesizable AXI4-Stream SV componentsAndrew Moch2020-06-251-0/+82