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* b200: Removed all AD9361 related firmwareAshish Chaudhari2014-08-126-2323/+0
| | | | | | | - FX3 does not respond to AD9361 firmware transaction VREQs - FX3 does not respond to AD9361 SPI transaction VREQs - Deleted all AD9361 firmware files - Bumped FW compat to 6
* b200: AD9361 firmware bugfixesAshish Chaudhari2014-08-011-0/+19
| | | | | | | | | | - Fix for BUG #485: B200: Channels Swap Between Runs # Added code to transition state machine out of FDD while reconfiguring active chains. # bb:0b9929 Mon Jun 16 14:56:26 2014 -0700 - Fix for BUG #500: B210: RX channels are not phase aligned # Set bit to invert RX if internal LNA is bypassed # bb:0a4565 Thu Jun 5 17:10:37 2014 -0700
* b200: Moved AD9361 driver to hostAshish Chaudhari2014-08-012-10/+13
| | | | | | | - Switched to FPGA SPI engine - Moved firmware AD9361 driver to UHD - Bumped FW compat to 5, FPGA compat to 4 - Known Issue: AD9361 SPI rate is too slow
* b2xx: Pulling FX3 and AD9361 source code into master.Ben Hilburn2014-04-076-0/+2301
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