uhd - Ettus' UHD Repository

	Commit message (Collapse)	Author	Age	Files	Lines
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\| * \|	Merge branch 'ise12' into u1e	Matt Ettus	2010-07-19	9	-45/+163
\| \|\ \ \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	* ise12: move declaration ahead of use put run_tx and run_rx on the displayed LEDs remove warnings add mux and demux to build mux multiple fifo streams into one. Allows priority or round robin split fifo into 2 streams based on first line in each packet precompute udp checksums barely fails timing on gigE/10 and gigE/12, larger fail on udp/10, but all seem to work ok
\| * \| \|	make loopback compile	Matt Ettus	2010-07-14	1	-0/+3
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\| * \| \|	Merge branch 'reload' into u1e	Matt Ettus	2010-07-09	2	-5/+10
\| \|\ \ \ \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	* reload: fix to stop endless error packets updated tests to match new features
\| * \| \| \|	point to new location for fifos	Matt Ettus	2010-07-09	1	-1/+1
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\| * \| \| \|	Merge branch 'reload' into u1e	Matt Ettus	2010-07-08	1	-11/+32
\| \|\ \ \ \ \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	* reload: error packets are now valid Extension Context packets
\| * \ \ \ \	Merge branch 'reload' into u1e	Matt Ettus	2010-07-07	1	-5/+16
\| \|\ \ \ \ \ \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	* reload: reload bit for vita rx ctrl
\| * \ \ \ \ \	Merge branch 'master' into u1e	Matt Ettus	2010-07-06	1	-4/+5
\| \|\ \ \ \ \ \ \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	* master: fix bug which caused serdes fifo to disappear
\| * \ \ \ \ \ \	Merge branch 'master' into u1e	Matt Ettus	2010-06-18	1	-1/+2
\| \|\ \ \ \ \ \ \ \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	* master: proper dependency tracking for the makefile
\| * \| \| \| \| \| \| \|	added ability to clear out fifos of tx and rx.	Matt Ettus	2010-06-17	3	-28/+37
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\| * \| \| \| \| \| \| \|	Merge branch 'master' into u1e_newbuild	Matt Ettus	2010-06-14	42	-715/+672
\| \|\ \ \ \ \ \ \ \ \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Made so Makefile changes as well to get it to build * master: new make works on ise12 produces good bin files first attempt at cleaning up the build system get rid of debug stuff to help timing move u2_core into u2_rev3 directory to simplify directory structure and save headaches Conflicts: usrp2/fifo/fifo36_to_fifo18.v usrp2/top/u2_rev3/Makefile usrp2/top/u2_rev3/Makefile.udp usrp2/top/u2_rev3/u2_core_udp.v
\| * \| \| \| \| \| \| \| \|	debug pins	Matt Ettus	2010-06-10	1	-3/+6
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\| * \| \| \| \| \| \| \| \|	much bigger fifos	Matt Ettus	2010-06-10	1	-2/+2
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\| * \| \| \| \| \| \| \| \|	left something out of the sensitivity list.	Matt Ettus	2010-06-10	1	-1/+1
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\| * \| \| \| \| \| \| \| \|	proper overrun, underrun connections, debug pins.	Matt Ettus	2010-06-10	1	-4/+8
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\| * \| \| \| \| \| \| \| \|	ignores	Matt Ettus	2010-06-08	1	-0/+1
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\| * \| \| \| \| \| \| \| \|	debug pins	Matt Ettus	2010-06-08	3	-4/+10
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\| * \| \| \| \| \| \| \| \|	Merge branch 'master' into u1e	Matt Ettus	2010-06-08	3	-15/+17
\| \|\ \ \ \ \ \ \ \ \ \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	* master: allow other clock rates in vita time report ise version in build proper name for directory name build directory with ISE version name
\| * \| \| \| \| \| \| \| \| \|	remove double declaration	Matt Ettus	2010-06-06	1	-1/+1
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\| * \| \| \| \| \| \| \| \| \|	use fifo19 not fifo18 in makefile	Matt Ettus	2010-06-06	1	-1/+1
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\| * \| \| \| \| \| \| \| \| \|	added little endian capability for gpmc to fifo and fifo to gpmc, since ARM ↵	Matt Ettus	2010-06-06	4	-41/+51
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	is LE.
\| * \| \| \| \| \| \| \| \| \|	get rid of redundant fifo18, since we can just use fifo19 and ignore the occ bit	Matt Ettus	2010-06-06	3	-44/+6
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\| * \| \| \| \| \| \| \| \| \|	Phil wants gpio #145	Matt Ettus	2010-06-03	2	-4/+4
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\| * \| \| \| \| \| \| \| \| \|	use same version as usrp2-udp, so regs are same place in memory map	Matt Ettus	2010-06-01	2	-2/+2
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\| * \| \| \| \| \| \| \| \| \|	Merge branch 'ise12_exp' into u1e	Matt Ettus	2010-06-01	11	-391/+1749
\| \|\ \ \ \ \ \ \ \ \ \ \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	* ise12_exp: zero out debug pins. helps timing a little bit. non-udp uses a different address for the tx dsp core manual merge to use localparams from udp version from UDP branch, changed names because I want these separate from the non-udp versions ignore output files new files from udp branch added to main Makefile change the debug pins, which makes it more reliable. This is unnerving. experimental mods to make ram loader fully synchronous. Based on IJB's work fixes from IJB from 5/24. Basically connect unconnected wires. removes the icache and pipelines the reads
\| \| * \| \| \| \| \| \| \| \| \|	zero out debug pins. helps timing a little bit.	Matt Ettus	2010-06-01	1	-9/+11
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\| \| * \| \| \| \| \| \| \| \| \|	Merge branch 'new_ramloader' into nocache_plus_newramloader, plus manual ↵	Matt Ettus	2010-05-28	4	-250/+280
\| \| \|\ \ \ \ \ \ \ \ \ \ \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	merge into udp version. Raw ethernet, ISE 10 -- Passes timing, works UDP, ISE 10 -- barely fails timing, works ISE 12 -- both fail timing, not tested yet. * new_ramloader: experimental mods to make ram loader fully synchronous. Based on IJB's work
\| \| \| * \| \| \| \| \| \| \| \| \|	experimental mods to make ram loader fully synchronous. Based on IJB's work	Matt Ettus	2010-05-26	3	-235/+266
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\| \| * \| \| \| \| \| \| \| \| \| \|	Merge branch 'master_nocache' into master_nocache_post_merge	Matt Ettus	2010-05-28	7	-26/+114
\| \| \|\ \ \ \ \ \ \ \ \ \ \ \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Seems to work on raw ethernet version which was automatically merged UDP version untested, and the following files were merged manually: u2_core_udp.v Makefile.udp * master_nocache: change the debug pins, which makes it more reliable. This is unnerving. fixes from IJB from 5/24. Basically connect unconnected wires. removes the icache and pipelines the reads
\| \| \| * \| \| \| \| \| \| \| \| \| \|	change the debug pins, which makes it more reliable. This is unnerving.	Matt Ettus	2010-05-26	1	-1/+2
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\| \| \| * \| \| \| \| \| \| \| \| \|	fixes from IJB from 5/24. Basically connect unconnected wires.	Matt Ettus	2010-05-24	2	-2/+5
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\| \| \| * \| \| \| \| \| \| \| \| \|	removes the icache and pipelines the reads	Matt Ettus	2010-05-20	5	-16/+98
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\| * \| \| \| \| \| \| \| \| \| \| \|	connect the rx run lines so it doesn't get optimized out	Matt Ettus	2010-06-01	1	-1/+4
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\| * \| \| \| \| \| \| \| \| \| \| \|	use DDR regs instead of a 2nd clock	Matt Ettus	2010-06-01	1	-8/+46
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\| * \| \| \| \| \| \| \| \| \| \| \|	assign addresses for the settings regs	Matt Ettus	2010-06-01	1	-5/+6
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\| * \| \| \| \| \| \| \| \| \| \| \|	vita49 tx and rx added in, all sample rates now at main system clock rate.	Matt Ettus	2010-06-01	4	-107/+220
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\| * \| \| \| \| \| \| \| \| \| \| \|	Merge branch 'udp' into u1e_merge_with_udp	Matt Ettus	2010-05-27	4	-172/+72
\| \|\ \ \ \ \ \ \ \ \ \ \ \ \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	* udp: better test program for just the tx side fix typo, no functionality difference ignores move dsp settings regs to reclocked setting bus. Works, gets us to within 18ps of passing timing reverting logic clean up which should have made timing better, but made it worse instead Conflicts: usrp2/control_lib/settings_bus.v usrp2/top/u2_core/u2_core.v
\| * \ \ \ \ \ \ \ \ \ \ \ \	Merge branch 'master' into u1e_merge_with_master	Matt Ettus	2010-05-27	235	-2409/+30
\| \|\ \ \ \ \ \ \ \ \ \ \ \ \ \| \| \| \|_\|/ / / / / / / / / / \| \| \|/\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	* master: get rid of some warnings by declaring setting reg width added width parameter to avoid warnings (thanks IJB) and default value parameter added pragmas suggested by Ian Buckley to help ISE12 synthesis get rid of old CVS linkage settings bus to dsp_clk now uses clock crossing fifo remove files for old prototypes, they were confusing people revert commit 9899b81f920 which should have improved timing but didn't Conflicts: usrp2/control_lib/setting_reg.v usrp2/top/u2_core/u2_core.v usrp2/top/u2_rev3/Makefile
\| * \| \| \| \| \| \| \| \| \| \| \| \|	test full width packets	Matt Ettus	2010-05-24	1	-0/+27
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\| * \| \| \| \| \| \| \| \| \| \| \| \|	fifo36_to_ll8 and fifo pacer need a real fifo between them or they deadlock ↵	Matt Ettus	2010-05-21	1	-1/+8
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	(by design)
\| * \| \| \| \| \| \| \| \| \| \| \| \|	fix double declaration	Matt Ettus	2010-05-21	1	-1/+0
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\| * \| \| \| \| \| \| \| \| \| \| \| \|	send bigger packets to reduce cpu load	Matt Ettus	2010-05-20	2	-3/+3
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\| * \| \| \| \| \| \| \| \| \| \| \| \|	put over/underrun on debug bus, remove high order address bits	Matt Ettus	2010-05-20	1	-1/+2
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\| * \| \| \| \| \| \| \| \| \| \| \| \|	Merge branch 'u1e' of ettus.sourcerepo.com:ettus/fpgapriv into u1e	Matt Ettus	2010-05-20	1	-4/+2
\| \|\ \ \ \ \ \ \ \ \ \ \ \ \ \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Conflicts: usrp2/top/u1e/u1e_core.v
\| \| * \| \| \| \| \| \| \| \| \| \| \| \|	better debug pins	Matt Ettus	2010-05-17	1	-6/+4
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\| * \| \| \| \| \| \| \| \| \| \| \| \| \|	combined timed and crc cases. fifo pacer produces/consumes at a fixed rate	Matt Ettus	2010-05-20	3	-34/+48
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\| * \| \| \| \| \| \| \| \| \| \| \| \|	moved fifos into gpmc_async, reorganized top level a bit, added in crc ↵	Matt Ettus	2010-05-12	6	-66/+144
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	packet gen and test
\| * \| \| \| \| \| \| \| \| \| \| \| \|	add missing signal from sensitivity list	Matt Ettus	2010-05-12	1	-1/+1
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\| * \| \| \| \| \| \| \| \| \| \| \| \|	Merge branch 'master' into u1e	Matt Ettus	2010-05-12	17	-46/+587
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\| * \| \| \| \| \| \| \| \| \| \| \| \| \|	packet generator and verifier, to test gpmc and other data transfer stuff	Matt Ettus	2010-05-12	4	-0/+153
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\| * \| \| \| \| \| \| \| \| \| \| \| \| \|	switched passthru of cgen_sen_b to gpio127, made a note of it. No more ↵	Matt Ettus	2010-05-10	8	-561/+9
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	safe_u1e necessary.