moved fifos into gpmc_async, reorganized top level a bit, added in crc packet gen and test

6 files changed, 144 insertions, 66 deletions

diff --git a/usrp2/control_lib/newfifo/packet_generator32.v b/usrp2/control_lib/newfifo/packet_generator32.v
new file mode 100644
index 000000000..6f8004964
--- /dev/null
+++ b/usrp2/control_lib/newfifo/packet_generator32.v
@@ -0,0 +1,21 @@
+
+
+module packet_generator32
+  (input clk, input reset, input clear,
+   output [35:0] data_o, output src_rdy_o, input dst_rdy_i);
+
+   wire [7:0] 	     ll_data;
+   wire 	     ll_sof, ll_eof, ll_src_rdy, ll_dst_rdy_n;
+   
+   packet_generator pkt_gen
+     (.clk(clk), .reset(reset), .clear(clear),
+      .data_o(ll_data), .sof_o(ll_sof), .eof_o(ll_eof),
+      .src_rdy_o(ll_src_rdy), .dst_rdy_i(~ll_dst_rdy_n));
+
+   ll8_to_fifo36 ll8_to_f36
+     (.clk(clk), .reset(reset), .clear(clear),
+      .ll_data(ll_data), .ll_sof_n(~ll_sof), .ll_eof_n(~ll_eof),
+      .ll_src_rdy_n(~ll_src_rdy), .ll_dst_rdy_n(ll_dst_rdy_n),
+      .f36_data(data_o), .f36_src_rdy_o(src_rdy_o), .f36_dst_rdy_i(dst_rdy_i));
+   
+endmodule // packet_generator32
diff --git a/usrp2/control_lib/newfifo/packet_verifier.v b/usrp2/control_lib/newfifo/packet_verifier.v
index 22c924198..b49ad1bbb 100644
--- a/usrp2/control_lib/newfifo/packet_verifier.v
+++ b/usrp2/control_lib/newfifo/packet_verifier.v
@@ -7,28 +7,26 @@
 
 module packet_verifier
   (input clk, input reset, input clear,
-   input [7:0] data_i, input sof_i, output eof_i, input src_rdy_i, output dst_rdy_o,
+   input [7:0] data_i, input sof_i, input eof_i, input src_rdy_i, output dst_rdy_o,
 
    output reg [31:0] total, 
    output reg [31:0] crc_err, 
    output reg [31:0] seq_err, 
    output reg [31:0] len_err);
 
-   assign dst_rdy_o = ~last_byte_d1;
-
    reg [31:0] 	     seq_num;
    reg [31:0] 	     length;
+   wire 	     first_byte, last_byte;
+   reg 		     second_byte, last_byte_d1;
 
    wire 	     calc_crc = src_rdy_i & dst_rdy_o;
    
    crc crc(.clk(clk), .reset(reset), .clear(last_byte_d1), .data(data_i), 
 	   .calc(calc_crc), .crc_out(), .match(match_crc));
 
-   wire 	     first_byte, last_byte;
-   reg 		     second_byte, last_byte_d1;
-
    assign first_byte = src_rdy_i & dst_rdy_o & sof_i;
    assign last_byte = src_rdy_i & dst_rdy_o & eof_i;
+   assign dst_rdy_o = ~last_byte_d1;
 
    // stubs for now
    wire 	     match_seq = 1;
diff --git a/usrp2/control_lib/newfifo/packet_verifier32.v b/usrp2/control_lib/newfifo/packet_verifier32.v
new file mode 100644
index 000000000..065607b6c
--- /dev/null
+++ b/usrp2/control_lib/newfifo/packet_verifier32.v
@@ -0,0 +1,23 @@
+
+
+module packet_verifier32
+  (input clk, input reset, input clear,
+   input [35:0] data_i, input src_rdy_i, output dst_rdy_o,
+   output [31:0] total, output [31:0] crc_err, output [31:0] seq_err, output [31:0] len_err);
+
+   wire [7:0] 	     ll_data;
+   wire 	     ll_sof_n, ll_eof_n, ll_src_rdy_n, ll_dst_rdy;
+   
+   fifo36_to_ll8 f36_to_ll8
+     (.clk(clk), .reset(reset), .clear(clear),
+      .f36_data(data_i), .f36_src_rdy_i(src_rdy_i), .f36_dst_rdy_o(dst_rdy_o),
+      .ll_data(ll_data), .ll_sof_n(ll_sof_n), .ll_eof_n(ll_eof_n),
+      .ll_src_rdy_n(ll_src_rdy_n), .ll_dst_rdy_n(~ll_dst_rdy));
+   
+   packet_verifier pkt_ver
+     (.clk(clk), .reset(reset), .clear(clear),
+      .data_i(ll_data), .sof_i(~ll_sof_n), .eof_i(~ll_eof_n),
+      .src_rdy_i(~ll_src_rdy_n), .dst_rdy_o(ll_dst_rdy),
+      .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err));
+
+endmodule // packet_verifier32
diff --git a/usrp2/gpmc/gpmc_async.v b/usrp2/gpmc/gpmc_async.v
index dd06478b3..380689c62 100644
--- a/usrp2/gpmc/gpmc_async.v
+++ b/usrp2/gpmc/gpmc_async.v
@@ -1,37 +1,38 @@
 //////////////////////////////////////////////////////////////////////////////////
 
 module gpmc_async
-  (// GPMC signals
-   input arst,
-   input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE,
-   input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE,
-   
-   // GPIOs for FIFO signalling
-   output rx_have_data, output tx_have_space, output reg bus_error, input bus_reset,
-   
-   // Wishbone signals
-   input wb_clk, input wb_rst,
-   output [10:0] wb_adr_o, output [15:0] wb_dat_mosi, input [15:0] wb_dat_miso,
-   output [1:0] wb_sel_o, output wb_cyc_o, output wb_stb_o, output wb_we_o, input wb_ack_i,
+  #(parameter TXFIFOSIZE = 11, parameter RXFIFOSIZE = 11)
+   (// GPMC signals
+    input arst,
+    input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE,
+    input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE,
+    
+    // GPIOs for FIFO signalling
+    output rx_have_data, output tx_have_space, output reg bus_error, input bus_reset,
+    
+    // Wishbone signals
+    input wb_clk, input wb_rst,
+    output [10:0] wb_adr_o, output [15:0] wb_dat_mosi, input [15:0] wb_dat_miso,
+    output [1:0] wb_sel_o, output wb_cyc_o, output wb_stb_o, output wb_we_o, input wb_ack_i,
+    
+    // FIFO interface
+    input fifo_clk, input fifo_rst,
+    output [35:0] tx_data_o, output tx_src_rdy_o, input tx_dst_rdy_i,
+    input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o,
+    
+    input [15:0] tx_frame_len, output [15:0] rx_frame_len,
+    
+    output [31:0] debug
+    );
 
-   // FIFO interface
-   input fifo_clk, input fifo_rst,
-   output [35:0] tx_data_o, output tx_src_rdy_o, input tx_dst_rdy_i,
-   input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o,
-
-   input [15:0] tx_frame_len, output [15:0] rx_frame_len,
+   wire 	  EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6));
+   wire [15:0] 	  EM_D_fifo;
+   wire [15:0] 	  EM_D_wb;
    
-   output [31:0] debug
-   );
-
-   wire 	EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6));
-   wire [15:0] 	EM_D_fifo;
-   wire [15:0] 	EM_D_wb;
-
    assign EM_D = ~EM_output_enable ? 16'bz : ~EM_NCS4 ? EM_D_fifo : EM_D_wb;
-
-   wire 	bus_error_tx, bus_error_rx;
-
+   
+   wire 	  bus_error_tx, bus_error_rx;
+   
    always @(posedge fifo_clk)
      if(fifo_rst)
        bus_error <= 0;
@@ -45,9 +46,11 @@ module gpmc_async
    // ////////////////////////////////////////////
    // TX Data Path
 
-   wire [17:0] 	tx18_data, tx18b_data;
-   wire 	tx18_src_rdy, tx18_dst_rdy, tx18b_src_rdy, tx18b_dst_rdy;
-   wire [15:0] 	tx_fifo_space;
+   wire [17:0] 	  tx18_data, tx18b_data;
+   wire 	  tx18_src_rdy, tx18_dst_rdy, tx18b_src_rdy, tx18b_dst_rdy;
+   wire [15:0] 	  tx_fifo_space;
+   wire [35:0] 	  tx36_data;
+   wire 	  tx36_src_rdy, tx36_dst_rdy;
    
    gpmc_to_fifo_async gpmc_to_fifo_async
      (.EM_D(EM_D), .EM_NBE(EM_NBE), .EM_NCS(EM_NCS4), .EM_NWE(EM_NWE),
@@ -64,18 +67,30 @@ module gpmc_async
    fifo19_to_fifo36 f19_to_f36
      (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
       .f19_datain({1'b0,tx18b_data}), .f19_src_rdy_i(tx18b_src_rdy), .f19_dst_rdy_o(tx18b_dst_rdy),
-      .f36_dataout(tx_data_o), .f36_src_rdy_o(tx_src_rdy_o), .f36_dst_rdy_i(tx_dst_rdy_i));
+      .f36_dataout(tx36_data), .f36_src_rdy_o(tx36_src_rdy), .f36_dst_rdy_i(tx36_dst_rdy));
    
+   fifo_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_fifo36
+     (.clk(wb_clk), .reset(wb_rst), .clear(0),
+      .datain(tx36_data), .src_rdy_i(tx36_src_rdy), .dst_rdy_o(tx36_dst_rdy),
+      .dataout(tx_data_o), .src_rdy_o(tx_src_rdy_o), .dst_rdy_i(tx_dst_rdy_i));
+
    // ////////////////////////////////////////////
    // RX Data Path
-
-   wire [17:0] 	rx18_data, rx18b_data;
-   wire 	rx18_src_rdy, rx18_dst_rdy, rx18b_src_rdy, rx18b_dst_rdy;
-   wire [15:0] 	rx_fifo_space;
    
+   wire [17:0] 	  rx18_data, rx18b_data;
+   wire 	  rx18_src_rdy, rx18_dst_rdy, rx18b_src_rdy, rx18b_dst_rdy;
+   wire [15:0] 	  rx_fifo_space;
+   wire [35:0] 	  rx36_data;
+   wire 	  rx36_src_rdy, rx36_dst_rdy;
+   
+   fifo_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_fifo36
+     (.clk(wb_clk), .reset(wb_rst), .clear(0),
+      .datain(rx_data_i), .src_rdy_i(rx_src_rdy_i), .dst_rdy_o(rx_dst_rdy_o),
+      .dataout(rx36_data), .src_rdy_o(rx36_src_rdy), .dst_rdy_i(rx36_dst_rdy));
+
    fifo36_to_fifo18 f18_to_f36
      (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
-      .f36_datain(rx_data_i), .f36_src_rdy_i(rx_src_rdy_i), .f36_dst_rdy_o(rx_dst_rdy_o),
+      .f36_datain(rx36_data), .f36_src_rdy_i(rx36_src_rdy), .f36_dst_rdy_o(rx36_dst_rdy),
       .f18_dataout(rx18_data), .f18_src_rdy_o(rx18_src_rdy), .f18_dst_rdy_i(rx18_dst_rdy) );
 
    fifo_cascade #(.WIDTH(18), .SIZE(12)) rx_fifo
@@ -106,6 +121,6 @@ module gpmc_async
       .wb_sel_o(wb_sel_o), .wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_we_o(wb_we_o),
       .wb_ack_i(wb_ack_i) );
    
-      assign debug = 0;
+   assign debug = 0;
    
 endmodule // gpmc_async
diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile
index 2aebb33f9..8622b8480 100644
--- a/usrp2/top/u1e/Makefile
+++ b/usrp2/top/u1e/Makefile
@@ -111,6 +111,10 @@ control_lib/newfifo/fifo_cascade.v \
 control_lib/newfifo/fifo36_to_ll8.v \
 control_lib/newfifo/fifo36_to_fifo18.v \
 control_lib/newfifo/fifo19_to_fifo36.v \
+control_lib/newfifo/packet_generator.v \
+control_lib/newfifo/packet_verifier.v \
+control_lib/newfifo/packet_generator32.v \
+control_lib/newfifo/packet_verifier32.v \
 control_lib/longfifo.v \
 control_lib/shortfifo.v \
 control_lib/medfifo.v \
diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v
index a262184a8..903121832 100644
--- a/usrp2/top/u1e/u1e_core.v
+++ b/usrp2/top/u1e/u1e_core.v
@@ -1,4 +1,9 @@
 
+
+//`define LOOPBACK 1
+//`define TIMED 1
+`define CRC 1
+
 module u1e_core
   (input clk_fpga, input rst_fpga,
    output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
@@ -61,47 +66,59 @@ module u1e_core
 
 		    .tx_frame_len(tx_frame_len), .rx_frame_len(rx_frame_len),
 		    .debug(debug_gpmc));
-/*
+
+`ifdef LOOPBACK
    fifo_cascade #(.WIDTH(36), .SIZE(9)) loopback_fifo
      (.clk(wb_clk), .reset(wb_rst), .clear(0),
       .datain(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy),
       .dataout(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy));
-*/
-   wire 	 tx_strobe, rx_strobe, tx_enable, rx_enable;
+   wire 	 rx_sof = rx_data[32];
+   wire 	 rx_eof = rx_data[33];
+`endif // LOOPBACK
+
+`ifdef TIMED
    wire [7:0] 	 rate;
-   wire 	 tx_fifo_rdy, rx_fifo_rdy;
-   
+
+   // TX side
+   wire 	 tx_enable;
    cic_strober tx_strober (.clock(wb_clk), .reset(wb_rst), .enable(tx_enable),
-			   .rate(rate), .strobe_fast(1), .strobe_slow(tx_strobe));
-   
-   fifo_cascade #(.WIDTH(36), .SIZE(11)) tx_fifo
-     (.clk(wb_clk), .reset(wb_rst), .clear(0),
-      .datain(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy),
-      .dataout(), .src_rdy_o(tx_fifo_rdy), .dst_rdy_i(tx_strobe));
+			   .rate(rate), .strobe_fast(1), .strobe_slow(tx_dst_rdy));
 
-   
+   // RX side
+   wire 	 rx_enable;
    reg [15:0] 	 ctr;
    wire [15:0] 	 rx_pkt_len = 480;
    wire 	 rx_eof = (ctr == rx_pkt_len);
    wire 	 rx_sof = (ctr == 0);
    
    cic_strober rx_strober (.clock(wb_clk), .reset(wb_rst), .enable(rx_enable),
-			   .rate(rate), .strobe_fast(1), .strobe_slow(rx_strobe));
+			   .rate(rate), .strobe_fast(1), .strobe_slow(rx_src_rdy));
    
-   fifo_cascade #(.WIDTH(36), .SIZE(11)) rx_fifo
-     (.clk(wb_clk), .reset(wb_rst), .clear(0),
-      .datain({2'b00,rx_eof,rx_sof,16'd0,ctr}), .src_rdy_i(rx_strobe), .dst_rdy_o(rx_fifo_rdy),
-      .dataout(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy));
-
    always @(posedge wb_clk)
      if(wb_rst)
        ctr <= 0;
-     else if(rx_strobe & rx_fifo_rdy)
+     else if(rx_dst_rdy & rx_src_rdy)
        if(ctr == rx_pkt_len)
 	 ctr <= 0;
        else
 	 ctr <= ctr + 1;
-   
+
+   assign rx_data = {2'b00,rx_eof,rx_sof,~ctr,ctr};   
+`endif // TIMED
+
+`ifdef CRC
+   packet_generator32 pktgen32
+     (.clk(wb_clk), .reset(wb_rst), .clear(clear),
+      .data_o(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy));
+
+   packet_verifier32 pktver32
+     (.clk(wb_clk), .reset(wb_rst), .clear(clear),
+      .data_i(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy),
+      .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err));
+
+   wire 	 rx_sof = rx_data[32];
+   wire 	 rx_eof = rx_data[33];
+`endif // CRC   
    
    // /////////////////////////////////////////////////////////////////////////////////////
    // Wishbone Intercon, single master
@@ -364,8 +381,8 @@ module u1e_core
    
    
    assign debug_gpio_0 = { debug_gpmc };
-   assign debug_gpio_1 = { {rx_enable, rx_strobe, rx_fifo_rdy, rx_strobe & ~rx_fifo_rdy},
-			   {tx_enable, tx_strobe, tx_fifo_rdy, tx_strobe & ~tx_fifo_rdy},
+   assign debug_gpio_1 = { {rx_enable, rx_src_rdy, rx_dst_rdy, rx_src_rdy & ~rx_dst_rdy},
+			   {tx_enable, tx_src_rdy, tx_dst_rdy, tx_dst_rdy & ~tx_src_rdy},
 			   {rx_sof, rx_eof, rx_src_rdy, rx_dst_rdy, rx_data[33:32],2'b0},
 			   {3'b0, bus_error, misc_gpio[11:0]} };