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| | | * | | Added to DCM's and some BUFG's to align the internal 125MHz clock edge with ↵Ian Buckley2010-11-114-5/+100
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | its presentation externally at the NoBL SRAM. Since we don't have a board level trace to use to estimate clock propigation delay we just loop through the I/O on the FPGA. This hasn't been verified as working on a USRP2 yet.
| | | * | | Enhanced test bench to be more like real world applicationIan Buckley2010-11-112-7/+14
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| | | * | | hangedddddddextrnal fifo size to use full NoBL SRAMianb2010-11-111-1/+1
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| | | * | | Corrected extfifo code so that all registers that are on SRAM signals are ↵ianb2010-11-115-46/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | packed into IOBs Explcit drives and skews added to GPIO pins Corrected minor error in FIFO logic that showed data avail internally incorrectly
| | | * | | capacity logic fixMatt Ettus2010-11-111-1/+1
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| | | * | | Added capacity to the module pinoutIan Buckley2010-11-111-3/+4
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| | | * | | Added a bunch of debug signals.Ian Buckley2010-11-114-9/+19
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| | | * | | Regenerated FIFO with lower trigger level for almost full flag to reflect ↵Ian Buckley2010-11-118-236/+113
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | logic removed from nobl_fifo. Improved ext_fifo_tb further, try to simulate more combinations of decomation rates and packet arrival patterns. Strip out the logic in nobl_fifo that made it look like a Xilinx fall-through FIFO...it is now very simple logic but a propriatory interface that exposes the high inetrnal latency of reads. Allow the USED size of the external FIFO to be parameterized from the core level. Currently set at only 256 Corrected a bug in vita_tx_deframer.v that can write to a FIFO when its full causing illegal state. Made further edits that are currently commented becuase simulation indicates they cause problems, however suspect a further bug is in this code.
| | | * | | Regenerated FIFO's for extfifo.Ian Buckley2010-11-1111-726/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are problems with certain configurations it seems. It is important that the fifo_xlnx_512x36_2clk_18to36 is generated with the "almost_full" pin even though it is not used in the application. if this pin is omitted the FPGA image doesn't work correctly
| | | * | | Edited FIFO instance to delete port that was not regenerated after ↵Ian Buckley2010-11-111-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | reconfiguration
| | | * | | Adding in files that probably didn;t exist in the ISE10.1 version of coregenIan Buckley2010-11-115-0/+808
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| | | * | | Bringing all coregen files checked in into syncIan Buckley2010-11-1110-137/+60
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| | | * | | Found bug due to not accounting for the correct number of possible in flight ↵Ian Buckley2010-11-117-52/+110
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | READ operations that can be in the extfifo pipeline. Regenerated fifo_xlnx_512x36_2clk_18to36 to include prog_full output triggered at 1017 so that there are 6 empty spaces to accept in flight read data upon completion. Had to generate the FIFO using Coregen from ISE12.1 due to 10.1 verion not working correctly in FPGA Still have to tackle making this simulate in Icarus
| | | * | | checkin of generated coregen filesMatt Ettus2010-11-1118-8/+556
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| | | * | | External FIFO tested in simulation and on USRP2 from decimation 64->8 with ↵Ian Buckley2010-11-1118-236/+7297
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | current head UHD code. Apparently operation is "flawless" but more regression and corner case regression could and should be done. Tristate drivers have been added at the top level of the hierarchy for the SRAM databus as is considered good practice for both Xilinx and ASIC design flows and so both top level and core fils have been touched.
| | | * | | Checkpoint checkin.Ian Buckley2010-11-1113-0/+1507
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Loopback is running via the external ZBT SRAM...HOWEVER, its not running well, its stable but the data is corrupted sometimes. Not clear if its a logic or AC timing/SI issue yet.
| | | * | | get it to buildMatt Ettus2010-11-115-5/+309
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| | | * | | moved forward from the old branchMatt Ettus2010-11-118-4/+876
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| | | * | | reverting part of the reversion of the spi settings.Matt Ettus2010-11-101-2/+2
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| | | * | | u2p needs the bigger regs for some reasonMatt Ettus2010-11-101-4/+4
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| | | * | | need to enable both 16 and 32 bit spi interfaces -- 16 used in u1e, 32 in u2 ↵Matt Ettus2010-11-101-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | and u2p
| | | * | | occ needs to be 2 bits wide on a 36 bit fifo interface.Matt Ettus2010-11-101-1/+2
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| | | * | | Merge branch 'u1e' into merge_u1eMatt Ettus2010-11-1064-215/+3325
| | | |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * u1e: (130 commits) invert led signals because they are active low duh allow for CS to rise before, at the same time, or after OE better debug pins watch the ethernet chip select on our debug bus fix timing issue on DAC outputs with rev 2. This puts the whole system on a 90 degree phase shift send all gpmc signals to mictor updated pins to match rev2, removed dip switch, etc. seems to compile ok. pins are different on rev2 fixed makefile to compile with our new system add register to tell host about compatibility level and which image we are using move declaration to make loopback compile no need for protocol headers since we're not doing ethernet match the signal names in this design debug pins cleanup properly integrate the new tx chain catch up with tx_policy attach run_tx and run_rx to leds connect atr delay the q channel to make the channels line up on the AD9862 ... Conflicts: usrp2/control_lib/Makefile.srcs
| | | | * | | invert led signals because they are active lowMatt Ettus2010-11-091-1/+1
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| | | | * | | duhMatt Ettus2010-11-041-1/+1
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| | | * | | | remove old commented out codeMatt Ettus2010-11-092-184/+2
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| | | * | | | fix timing problem on DAC output busMatt Ettus2010-11-091-2/+2
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| | | * | | | U2P: Working ICAP bootloader. Should be ready for release.Nick Foster2010-10-081-224/+236
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| | | * | | | U2P: remember your semicolons.Nick Foster2010-10-071-1/+1
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| | | * | | | U2P: modified ICAP. turns out ICAP needs clock disabled while CE is not ↵Nick Foster2010-10-072-206/+238
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | asserted. which is the point of a CE, but... it works. Also committed latest bootloader, might not be final version.
| | | * | | | separate the bootloader image into another fileMatt Ettus2010-10-072-204/+205
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| | | * | | | U2P: newest bootloader with support for 32Mbit flashNick Foster2010-10-051-157/+196
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| | | * | | | Fixed PPS. Instantiation was miscapitalized.Nick Foster2010-08-271-1/+1
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| | | * | | | invert adc_a because it is inverted on schematic. Also clean up extraneousMatt Ettus2010-08-251-15/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | adc signals from old adc on U2
| | | * | | | SWAP DAC A and B, invert B to match schematicsMatt Ettus2010-08-251-3/+4
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| | | * | | | Use new tx_policy stuff, reassigned leds to be just like U2Matt Ettus2010-08-252-36/+34
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| | | * | | | Merge branch 'tx_policy' into u2p_txpolicyMatt Ettus2010-08-2513-5600/+333
| | | |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * tx_policy: (21 commits) clean up DAC inversion and swapping to match schematics Clean up iq swapping on RX. It is now swapped in the top level. widened muxes to 4 bits to match tx side and handle more ADCs in future rx error context packets should not be marked as errors in the fifo added compat number to usrp2 readback mux makefile dependency fix for second expansion provide a way to get out of the error state without processor intervention sequence number reset upon programming streamid attempt at avoiding infinite error messages implemented "next packet" and "next burst" policies sequence errors can happen on start of burst as well. more informative error codes cleaner error handling introduce new error types test mux and gen_context_pkt this is an output file, it shouldn't be checked in insert protocol engine flags when requested move the streamid so it isn't at the same address as clear_state connect the demux fix a typo tx error packets now muxed into the ethernet stream back to the host ...
| | | * | | | | Added a sanity checker Python script.Nick Foster2010-08-244-3/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The script just looks for input/inout/outputs that are declared in the .v but not in the .ucf. If it finds an occurrence, it aborts the compile. Removed pin "POR" from u2plus.v due to the script. Also reverted an error I introduced to test the script, which I mistakenly committed earlier.
| | | * | | | | Ensure ethernet LED pin has 12mA outputNick Foster2010-08-241-1/+1
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| | | * | | | | Added 12mA current spec to eth phy LED pin.Nick Foster2010-08-202-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Changed debug pins to debug ICAP instead of VITA -- which makes it actually meet timing, too. Bonus.
| | | * | | | | Fixed u2plus_core.v to use quad_uart instead of simple_uart.Nick Foster2010-08-121-1/+1
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| | | * | | | | quad uart instead of single, for the extra on board serial portsMatt Ettus2010-08-114-10/+82
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| | | * | | | | Added DCM reset line to sr.Nick Foster2010-07-291-3/+5
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| | | * | | | | Fix for SPI SS > 8 bits wideNick Foster2010-07-281-2/+2
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| | | * | | | | latest bootloader in core, fixed eth_led to be active high, connected eth clkNick Foster2010-07-282-39/+167
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| | | * | | | | Merge branch 'u2p' of ettus.sourcerepo.com:ettus/fpgapriv into u2pNick Foster2010-07-271-0/+4
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| | | | * | | | | capitalization matchingMatt Ettus2010-07-211-1/+5
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| | | * | | | | | fix timing races on ADC and DAC pinsNick Foster2010-07-271-10/+20
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| | | * | | | | reconnect the serial clockMatt Ettus2010-07-201-1/+1
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| | | * | | | | connect SPI to adc, correct capitalization of SEN pinsMatt Ettus2010-07-202-9/+11
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