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* rfnoc: fir filter: Add support for multiple channels to block controllerJonathon Pendlum2022-03-233-133/+218
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* mpm: speed up reading gps mboard sensorsDavid Raeman2022-03-231-13/+9
| | | | | | This commit uses a more performant buffered I/O approach for reading the gpsd socket. Previously, querying a gps mboard sensor on an mpm radio would take 300-500ms due to the loop reading one byte at a time.
* images: Update manifest and compat number for X410Humberto Jimenez2022-03-232-2/+2
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* test: add support for new benchmark_rate argsVirendra Kakade2022-03-232-8/+12
| | | | | | | | Add support for the new "priority" and "multi_streamer" benchmark_rate args to run_benchmark_rate.py to enable batch runs of benchmark_rate using those arguments. Signed-off-by: Virendra Kakade <virendra.kakade@ni.com>
* mpm: n3xx: Recommend reboot USRP after BISTAaron Rossetto2022-03-231-1/+4
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* host: devtest: Add GPIO tests for reading back ATR settingsLane Kolbly2022-03-232-1/+30
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* mpm: x4xx: Remove GPIO classic mode registerLane Kolbly2022-03-231-12/+2
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* host: x410: Emulate GPIO classic ATR mode using new modeLane Kolbly2022-03-233-13/+83
| | | | | | This fixes an issue with setting the active channel source in MPM, and additionally allows opening up the more flexible API in the future without requiring a filesystem update.
* host: x410: Cache GPIO source in mb_controllerLane Kolbly2022-03-233-1/+12
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* Fix handling of discontinuities in power calibration dataLars Amsel2022-03-237-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The power that corresponds to a certain gain values depends on the frequency band we are in. At the edges of these bands discontinuities can occur (the gain necessary to achieve the same power value changes non-continuously). The power calibration does a linear interpolation between two neighbor points in the calibration data set to find at best fitting value. We therefore have to make sure that this interpolation does not cross discontinuities. This is a minimal invasive approach. It adds values at discontinuities for the lower and the upper band. The power calibration format uses the frequency for a power to gain mapping as a map key. Therefore two gain to power mappings cannot be stored for the same frequency as it would be needed for the discontinuity. Instead the mapping for the lower band is stored at the discontinuity frequency itself. The mapping for the upper band is stored at the frequency + 1Hz. The calibration will therefore still fail to yield proper results within this sub-Hertz range. The frequency lookup in the power calibration manager now uses round instead of truncation to find the best mapping frequency in the calibration table. With this, searching for neighbor data points now ensures that the data points used belong to the same band (except for the range of (f_discontinuity, f_discontinuity + 1Hz) ). This commit does not solve the issue for calibration data generated with usrp_power_cal.py because the Python interface has no means to detect band edges for the USRP it is calibrating.
* fpga: e31x: Update DRAM IP simulationWade Fife2022-03-231-4/+22
| | | | | Update the simulation to use the renamed IP. Add ModelSim support.
* fpga: e31x: Fix DRAM traffic gen IP nameWade Fife2022-03-231-1/+1
| | | | | Change name in DRAM IP Makefile from IP_MIG_7SERIES_TG_SRCS to IP_DDR3_16BIT_TG_SRCS to match the naming of other variables.
* docs: Improve table on 'identification'Martin Braun2022-03-231-8/+8
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* fixup! docs: Update instructions for changing hostnameWade Fife2022-03-231-2/+2
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* docs: Update instructions for changing hostnameWade Fife2022-03-233-12/+12
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* docs: Update sfp port config locationWade Fife2022-03-232-4/+4
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* mpm: Factor out common code between E31x_db and Neon classesMartin Braun2022-03-175-314/+222
| | | | | These classes share a *lot* of common code, due to them both being AD9361-based devices. This code is now factored out into a single file.
* mpm: e3xx: Fix Pylint warnings in periph_mgr classesMartin Braun2022-03-172-14/+11
| | | | | | - Whitespace - Long lines - Superfluous imports
* host: Add power_reference_iface::sptr declarationLane Kolbly2022-03-171-0/+2
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* fpga: ci: Schedule weekly FPGA pipeline runHumberto Jimenez2022-03-161-0/+8
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* fpga: ci: Improve IP build cachingHumberto Jimenez2022-03-151-8/+20
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* fpga: ci: Add stages-based pipelineHumberto Jimenez2022-03-1513-271/+613
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* fpga: ci: Ignore objects in hwtoolsHumberto Jimenez2022-03-151-0/+2
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* fpga: tools: Add CG_400 image to X410 binaries packageHumberto Jimenez2022-03-151-0/+5
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* docs: Update manual for new X410 default targetsWade Fife2022-03-142-14/+18
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* fpga: x400: Add x410_400_128_rfnoc_image_coreWade Fife2022-03-145-3/+1613
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* docs: Fix Doxygen warningsMartin Braun2022-03-142-18/+5
| | | | | | - Removed variables that have been deprecated in newer Doxygen versions - Replaced <speedgrade> with $speedgrade in E310 manual; Doxygen thinks it's an HTML tag.
* python: Add __init__ to uhd.utilsMartin Braun2022-03-141-0/+0
| | | | | | | | | | | | | | | | | Without this, the following code fails: >>> import uhd >>> U = uhd.usrp.MultiUSRP("type=x4xx") >>> M = U.get_mpm_client() Traceback (most recent call last): File "<input>", line 1, in <module> M = U.get_mpm_client() File ".../uhd/usrp/multi_usrp.py", line 37, in <lambda> setattr(self, 'get_mpm_client', lambda: _get_mpm_client(token, mb_args)) File ".../uhd/usrp/multi_usrp.py", line 19, in _get_mpm_client from uhd.utils import mpmtools ModuleNotFoundError: No module named 'uhd.utils'
* host: Create meta_range_t::as_monotonicLane Kolbly2022-03-143-1/+62
| | | | | | | | In order to perform certain operations (start/stop/step), meta_range_t objects must be "monotonic", meaning that the subranges composing it are sorted and non-overlapping. This commit creates a method which takes a non-monotonic meta_range_t containing no non-continuous subranges and converts it into a monotonic meta_range_t.
* docs: Fix reference to RFNoC documentationMartin Braun2022-03-141-1/+7
| | | | This fixes links to RFNoC docs in the "Coding to the API" section.
* docs: rdtesting: Remove invalid rate configurationMartin Braun2022-03-141-1/+0
| | | | | Removes an invalid rate configuration for N310 functional FPGA verification tests.
* host: test: Add UHD_UNITTEST_LOG_LEVEL overrideLane Kolbly2022-03-113-21/+55
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* docs: stream_args: Clarify usage of stream_args_t::channelsMartin Braun2022-03-111-15/+23
| | | | | This vector is no longer used with RFNoC devices. We remove references to X300 from the example, and instead use B210 as an example.
* rfnoc: Remove UHD3-API usagesMartin Braun2022-03-112-14/+0
| | | | | | | - rfnoc_replay_samples_from_file still had UHD3-vestiges for selecting block port and ID - The documentation for stream_args_t also included block port and ID examples
* images: Update manifest and compat number for X410Aaron Rossetto2022-03-102-2/+2
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* fpga: rfnoc: Fix PPS edge detectionmichael-west2022-03-091-1/+1
| | | | | | | Make timekeeper module sample rising edge instead of falling edge of PPS signal. Signed-off-by: michael-west <michael.west@ettus.com>
* docs: n3xx: Add info on customizable band edges and gain profilesMartin Braun2022-03-091-0/+45
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* fpga: rfnoc: Make Replay packet length independent of burst sizeWade Fife2022-03-092-106/+158
| | | | | | | | | | | | | Before this change, the packet size output by the Replay block during playback was limited to length of a full memory burst transaction. This led to relatively small packets during playback (typically 2 KiB) and had other side effects, such as simultaneous playback from two different memory locations using different packet sizes because of differences in memory alignment. With this change, the configured packet size, as set by the register REG_PLAY_WORDS_PER_PKT, is used for all packets except the last packet of playback, which can of course be smaller.
* fgpa: rfnoc: Set Replay memory transactions to 2 KiBWade Fife2022-03-092-7/+15
| | | | | | | This sets the Replay block's counter width so that memory bursts are up to 2 KiB. Previously, the counter width was fixed, which meant that wide memories would require especially large buffers and could exceed the 4 KiB limit imposed by AXI.
* fpga: Add SPDX license identifierAaron Rossetto2022-03-091-0/+2
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* rfnoc: radio: Explicitly set MTU forwarding policy to DROPMartin Braun2022-03-081-0/+1
| | | | | | | | | | | This is a follow-up to 930fa39, where we set the MTU property explicitly for several blocks. The radio block should also receive this treatment, as the IQ data going into its inputs is not forwarded to its outputs. This patch will remove spurious log messages like these: [INFO] [0/Radio#0] Setting default MTU forward policy. [INFO] [0/Radio#1] Setting default MTU forward policy.
* tests: Apply clang-format to convert_testAaron Rossetto2022-03-081-177/+259
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* tests: Fix converter benchmark disable on Boost <1.68Aaron Rossetto2022-03-081-0/+80
| | | | | | | | | | | | | | | | Boost versions prior to 1.68 appear to have a bug where a decorator to denote a test as disabled is not honored when affixed to a data-driven test case, which is how the benchmarks in convert_test are skipped when the unit test is run. (The tests take some time to complete and we don't want them running with every CI pass.) This commit adds an alternative benchmark skipping mechanism when Boost <1.68 is used. The benchmark test cases perform a runtime check for the user-provided `--benchmark` command-line option. If not found, the test case returns prematurely. If found, the test case will execute. Note that because `--benchmark` is a command-line option specific to this test, and not to Boost, the options must follow `--` in the command line in order to take effect: `convert_test -- --benchmark`.
* tests: Atomicize counters in benchmark_rateAaron Rossetto2022-03-071-10/+10
| | | | | | | | The counters that keep track of overruns, underruns, number of samples transferred, etc., were not atomic. Thus, running benchmark_rate with multiple threads would result in inaccurate statistics being reported at the end of the run. This commit makes those counters atomic variables so that they are updated properly.
* docs: x4xx: Add new FPGA image descriptionsWade Fife2022-03-041-20/+44
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* fpga: x400: Cleanup FPGA MakefileWade Fife2022-03-041-40/+61
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* fpga: x400: Add support for DRAM with 400 MHz BWWade Fife2022-03-042-22/+24
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* fpga: x400: Change AXI XB for DRAM to 512-bitWade Fife2022-03-041-106/+17
| | | | | | Change the width of the crossbar in the AXI Interconnect IP from 256-bit to 512-bit to match the DRAM memory controller width and to give better performance.
* fpga: rfnoc: Fix strobe probability in radio simulatorWade Fife2022-03-041-7/+7
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* fpga: rfnoc: Regenerate noc_shellsWade Fife2022-03-0419-30/+49
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