docs: Update manual for new X410 default targets

2 files changed, 18 insertions, 14 deletions

diff --git a/fpga/docs/usrp3/build_instructions.md b/fpga/docs/usrp3/build_instructions.md
index 235ed07ff..eea4bd71a 100644
--- a/fpga/docs/usrp3/build_instructions.md
+++ b/fpga/docs/usrp3/build_instructions.md
@@ -232,18 +232,8 @@ target type `X4_200` is configured for a 200 MHz analog bandwidth, and can
 support a 245.76 MHz or 250 MHz master clock rate.
 
 A more detailed description of the targets can be found at \ref x4xx_updating_fpga_types.
-The following targets are available through the Makefile:
-
-- `X1_100`
-- `X4_{100, 200}`
-- `XG_{100, 200}`
-- `X4_{100, 200}`
-
-The following bitstreams can be built, but are considered experimental:
-
-- `X4C_{100, 200}`
-- `C1_400`
-- `CG_{100, 400}`
+Run `make help` in the `<repo>/fpga/usrp3/top/x400/` directory to see
+the complete list of targets available.
 
 #### Outputs
 - `build/usrp_<product>_fpga.bit` : Configuration bitstream with header
@@ -252,10 +242,10 @@ The following bitstreams can be built, but are considered experimental:
 
 ### Additional Build Options
 
-It is possible to make a target and specify additional options in the form VAR=VALUE in
+It is possible to make a target and specify additional options in the form `VAR=VALUE` in
 the command. For example:
 
-$ make X310 GUI=1
+    $ make X310 GUI=1
 
 The options available are described in the following subsections.
 
diff --git a/host/docs/usrp_x4xx.dox b/host/docs/usrp_x4xx.dox
index a2c16ef12..7c561dde9 100644
--- a/host/docs/usrp_x4xx.dox
+++ b/host/docs/usrp_x4xx.dox
@@ -473,6 +473,20 @@ As of UHD 4.2, the following images flavors are shipped with UHD:
 | X4_200            | 200 MHz   | 4x 10 GbE (All Lanes)   | N/C                     | Yes     | Yes (4-Ch Replay)  |
 | CG_400            | 400 MHz   | 100 GbE                 | 100 GbE                 | No      | No                 |
 
+The following list shows some potential use-cases for different FPGA images:
+
+- `X4_200`: 200 MHz analog bandwidth, or below (using RFNoC DDC/DUCs),
+  streaming between the X410 and an external host computer, or streaming
+  to/from on-board DRAM using the RFNoC Record/Replay block.
+- `CG_400`: Full-rate (400 MHz analog bandwidth) streaming between the X410 and
+  an external host computer. The current implementation requires dual 100 GbE
+  connections for 4 full-duplex channels or a single 100 GbE connection for 2
+  full-duplex channels.
+- `X4_400`: Full-rate (400 MHz analog bandwidth) streaming to/from on-board
+  DRAM using the RFNoC Record/Replay block. Up to 4 x 10 GbE connections may be
+  used to access the DRAM from an external host computer. Note that 10 GbE is
+  not fast enough for continuous full-rate streaming at this rate.
+
 Run `make help` in the `fpga/usrp3/top/x400` directory of the UHD repository to
 see a complete list of FPGA images that can be built, some of which are
 experimental (unsupported).