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* uhd: cal: Add iq_cal calibration data container classMartin Braun2020-04-0217-1/+760
| | | | | | | | This class can be used to store calibration coefficients for the X300 DC offset and IQ imbalance calibration. Note: This also modifies Doxyfile.in to not document files generated by flatc.
* uhd: Add calibration container classMartin Braun2020-04-023-0/+68
| | | | | | | This adds uhd::usrp::cal::container, which serves as a base class for calibration data. It also provides the interp_mode enum class which can be useful for future calibration classes.
* fpga: tools: Add support for .sdc in VivadoPaul Butler2020-04-021-0/+3
| | | | | | viv_utils.tcl will now read files with the .sdc suffix using the read_xdc Vivado command. This is especially useful when I/O timing constraints in the FPGA and CPLD need to depend on a common constant.
* fpga: rfnoc: Add gate to dynamically enable control-port interfacesMax Köhler2020-04-011-0/+91
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* fpga: rfnoc: ctrport_combiner with deterministic latency for PRIORITY=1Max Köhler2020-04-011-13/+51
| | | | | The latency through the combiner is static if only one master interface is used and PRIORITY=1 is set.
* fpga: tools: Add default Vivado install locationWade Fife2020-04-011-1/+5
| | | | | | Xilinx changed the default Vivado install location from /opt/Xilix to /tools/Xilinx. This commit adds support for finding Vivado in either the new location or the old location.
* multi_usrp: Fix ALL_CHAN and ALL_MBOARDS API calls for Gen-3 devicesMartin Braun2020-03-311-105/+64
| | | | | | | | Most of the API calls that default an arg to ALL_CHANS or ALL_MBOARDS were in fact broken. This adds a macro to efficiently mux out API calls that take such wildcard arguments so we don't have to repeat the same loop all over the place, even for those API calls that already correctly implemented wildcards (for consistency).
* utils: uhd_usrp_probe: Output frontend infoMichael West2020-03-311-5/+13
| | | | | | Add output of frontend info for RFNoC devices. Signed-off-by: Michael West <michael.west@ettus.com>
* docs: Update Basic/LF dboard references to use new operating modemattprost2020-03-312-21/+31
| | | | | | | | | | | | | | | On the new RFNoC with UHD 4.0 architecture, Basic/LF dboards use a new operating paradigm. The streaming mode (real mode or complex) is determined by setting the antennas (to A/B or AB/BA respectively). Basic/LF RX dboards also support 2 frontends (0 and 1), and Basic/LF TX dboards support 1 frontend (0). This new behavior only applies to applicable RFNoC devices (currently X300/X310). All pre-RFNoC devices (i.e. USRP2/N200 and earlier) maintain legacy behavior. RFNoC with UHD 3.xx branches also maintains old behavior. Signed-off-by: mattprost <matt.prost@ni.com>
* examples: Change benchmark_rate default thread priorityAaron Rossetto2020-03-271-1/+1
| | | | | | | | | | | | | | | | | | This commit modifies the benchmark_rate example to use the operating system's default thread priority, instead of real-time thread priority, by default. UHD 4.0 includes a number of significant improvements to the streaming architecture that allow for best performance to be achieved without having to resort to elevating the process thread priority to real-time. Internal testing shows degraded streaming performance in common use cases (i.e. non-DPDK) when the process thread priority is set to real-time. It should be noted that applications which use DPDK may still experience better performance when the process thread priority is set to real-time. Users may continue to manually override the process thread priority in benchmark_rate using the --priority=high command-line option. The need to elevate the process thread priority will be application- and deployment-dependent.
* fixup! x300: lf/basic antenna API implementationMartin Braun2020-03-261-2/+2
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* uhd: cal: Add database classMartin Braun2020-03-2612-0/+542
| | | | | | This class contains methods to store and retrieve data from the local calibration database. Note that in this case, the "database" is just a bunch of files on the local filesystem.
* uhd: paths: Add get_cal_data_path() API callMartin Braun2020-03-263-1/+25
| | | | This points to the location where cal data is stored.
* fpga: tools: Add ModelSim to run_testbenches.pyWade Fife2020-03-231-11/+11
| | | | | This adds the "modelsim" simulator option to run_testbenches.py to allow for regression testing of the native ModelSim simulation target.
* fixup! fpga: tools: Add modelsim to make sim targetsWade Fife2020-03-231-27/+25
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* x300: lf/basic antenna API implementationmattprost2020-03-234-110/+234
| | | | | | | | | | | | | | | | This results in a change of operation for LF/Basic Boards on X300/X310 devices. The RX streaming mode will now be specified by the antenna rather than the subdev: (AB or BA for complex streaming, and A or B for real-mode streaming, with AB being the default antenna value). For real-mode streaming, data is collected as complex data with zeroed-out values in the quadrature domain. The subdevs for these boards have been changed to 0 and 1 for the RX channels, and 0 for the TX channel, in order to align with subdev specs of other RFNoC devices. Note: the old streaming mode paradigm is still in place for the N210.
* fpga: Fix errors found by linting with vsimAndrew Moch2020-03-236-19/+22
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* utils: uhd_images_downloader: use HTTPS instead of HTTP to avoid redirectMarcus Müller2020-03-201-1/+1
| | | | | | | | Since the webserver responding to requests at http://files.ettus.com replies with a redirect to the same URL, but using the https:// transport, this isn't only the safer thing we should be doing, anyways, but also the quicker, since it saves the user from one unnecessary redirect.
* fpga: tools: Add modelsim to make sim targetsAndrew Moch2020-03-204-35/+127
| | | | | | | | | | | | | | | This adds a simulation make target that allows you to run ModelSim natively rather than through Vivado. Adds or modifies the following simulation make targets: make vlint - Brake up compilation to Verilog/SystemVerilog/VHDL make modelsim - Depends on make vlint and invokes modelsim Adds the following variables: MODELSIM_ARGS - Added to invocation of ModelSim SVLOG_ARGS - Added to SystemVerilog invocation of vlog VLOG_ARGS - Added to Verilog invocation of vlog VHDL_ARGS - Added to VHDL invocation of vcom
* uhd: math: Add linear_interp()Martin Braun2020-03-182-7/+30
| | | | This lets you linearly interpolate between two points.
* debian: Rename control file for libuhd to contain 4.0.0 versionMartin Braun2020-03-181-0/+0
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* debian: Fixes to copyright fileMartin Braun2020-03-181-389/+385
| | | | | | - FindGit.cmake is no longer part of UHD, removed from copyright list - The file list includes FPGA code, which needs to be updated to point to fpga/ instead of fpga-src/
* cmake: Add CMakeRC module and ::rc namespaceMartin Braun2020-03-184-1/+665
| | | | | | | | | | | | | | | | | | | | | | | | | | This module allows to add binary files into UHD (e.g., for cal data storage) in a platform-independent way. The upstream CMakeRC.cmake is modified in the following way to allow linkage against a shared object: ```diff # Generate the actual static library. Each source file is just a single file # with a character array compiled in containing the contents of the # corresponding resource file. add_library(${name} STATIC ${libcpp}) set_property(TARGET ${name} PROPERTY CMRC_LIBDIR "${libdir}") set_property(TARGET ${name} PROPERTY CMRC_NAMESPACE "${ARG_NAMESPACE}") target_link_libraries(${name} PUBLIC cmrc::base) set_property(TARGET ${name} PROPERTY CMRC_IS_RESOURCE_LIBRARY TRUE) + set_property(TARGET ${name} PROPERTY POSITION_INDEPENDENT_CODE ON) ``` This forces the -fPIC flag for the static object that CMakeRC generates, allowing to link it into a shared object file. The version of CMakeRC used is: a7e355290, cloned from git@github.com:vector-of-bool/cmrc.git.
* lib: deps: Add FlatBuffers 1.11.0 header filesMartin Braun2020-03-1817-0/+9179
| | | | | | | | | | FlatBuffers is used to (de-)serialize calibration data. For most use cases, only a few headers are required, so we provide them with UHD instead of requiring all UHD users to install their own version of FlatBuffers. This adds the headers to host/lib/deps, and updates the Debian copyright file appropriately.
* lib: Use from_str<bool> in constrained_device_args_tAaron Rossetto2020-03-181-17/+7
| | | | | | | This modifies `constrained_device_args_t::bool_arg::parse()` to use `uhd::cast::from_str<bool>` to interpret strings as Boolean values, deduplicating the string parsing code and single-sourcing it from `uhd::cast`.
* utils: Add bool specialization to cast::from_str()Aaron Rossetto2020-03-183-0/+60
| | | | | | | This adds a specialization to `uhd::cast::from_str()` to handle `bool` as a target type and interpret strings like 'y', 'Y', 'n', 'No', 'True', 'False', etc. as Boolean values, as well as the traditional '0' and '1' (which also work).
* tests: Allow custom name for mock terminatorAaron Rossetto2020-03-131-4/+6
| | | | | | | Allow a unit test to instantiate a mock_terminator_t and provide a custom name to be displayed when get_unique_id() is called (generally for logging purposes). The custom name is optional and the generic 'MOCK_TERMINATOR' is used if unset.
* tests: Allow custom mock_reg_iface_t in mock blockAaron Rossetto2020-03-132-8/+10
| | | | | | Allow clients to pass a custom instance of a mock_reg_iface_t for use with mock_block_container. This is especially useful when a block test subclasses mock_reg_iface_t to implement specialized behaviors.
* fpga: tools: Ignore BD layout info for TCL-based BDHumberto Jimenez2020-03-121-1/+1
| | | | | | | | | | | | | | | | | | When using viv_modify_tcl_bd, two Vivado instances are open: 1. GUI-mode Vivado that opens a TCL-based BD for the user to edit. 2. Batch-mode Vivado that saves changes from (1) and rewrites the TCL source file. During (2), the previous tool implementation was saving layout information in the TCL source file. This layout info gets outdated when the BD is reopened, because (1) regenerates the layout to provide a clean BD diagram in the Vivado GUI. Furthermore, each time the BD is open, the layout information will vary due to Vivado's window size, thus creating untracked changes in the source TCL file. This commit removes the command option that requests Vivado to save layout information.
* utils: cal: Replace property tree accesses with other API callsMartin Braun2020-03-121-43/+35
| | | | | | | | | | The cal utils read the property tree to identify the daughterboard information (serial, type, etc.). The paths for properties have changed in UHD 4.0, causing these utilities to fail. Instead of conditionally parsing the property tree, this commit changes the utilities such that dictionaries are pulled out of the multi_usrp object, which work regardless of the device type.
* multi_usrp: Provide valid return value for multi_usrp::get_device()Martin Braun2020-03-123-8/+72
| | | | | | | | | | | | For RFNoC devices, multi_usrp::get_device() no longer returns a device pointer, rather, it returns a nullptr. This is intentional because access to the underlying device is no longer allowed. However, legacy code can segfault (e.g. portions ofr gr-uhd). This patch returns a faux uhd::device class, which almost mimicks the original behaviour perfectly, by redirecting its class methods back to multi_usrp_rfnoc. The only exception is recv_async_msg(), which requires a TX streamer. This function will always return false now.
* utils/C API: Fix property tree accessMartin Braun2020-03-123-8/+8
| | | | | | | | | | The introduction of multi_usrp_rfnoc caused multi_usrp::get_device()->get_tree() to segfault for gen3 devices. In defcb174, we introduced a fix for this (multi_usrp::get_tree()) but we didn't apply it to internal utilities. That means the uhd_cal_* utilties were broken, along with certain sections of the C API, and the latency test suite. This fixes the segfault issue.
* python: Export UHD paths utility functionsMartin Braun2020-03-123-0/+30
| | | | | | | | | All of the functions defined in uhd/utils/paths.hpp are now available in Python, with the exception of get_module_paths(). #!/usr/bin/env python3 import uhd print(uhd.get_lib_path()) # Prints location of libuhd
* python: Remove Python2-specific codeMartin Braun2020-03-121-7/+0
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* lib: gain_group: Remove spurious logsMartin Braun2020-03-121-2/+0
| | | | | | Whenever gains where set through a gain_group, it would output spurious log messages that must stem from someone's debug code, since the log messages are not very useful by themselves.
* python: Arrange file in Python module into uhd/ subdirectoryMartin Braun2020-03-108-21/+54
| | | | | | | | | | | | | | | This adds the host/python/uhd subdirectory, which will add all files that go into the actual Python module once installed. Before, all Python files were directly in host/python and got sorted into their appropriate destination folders during configuration and installation. This change doesn't change anything (Python modules will look the same as they do now), except that it makes the source tree a tad neater, but more importantly, it creates a consistent directory structure when adding submodules to the uhd module. Apart from the PyBind11-generated shared object file (which gets generated during build time), the uhd/ subdirectory in host/python exactly resembles the Python module once installed, so it's more obvious where to add new submodules and files.
* README.md: Update references to fpga-srcLane Kolbly2020-03-101-10/+2
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* sim: Rename class typedefsWade Fife2020-03-094-72/+72
| | | | | | | | For example, the ChdrPacket typedef is being renamed from ChdrPacket to ChdrPacket_t. This allows the code to distinguish between the unparameterized class and the already parameterized class. This isn't strictly necessary, but it makes some Vivado 2019.1 bugs easier to work around. It also makes the code slightly less ambiguous.
* sim: Add ChdrIfaceBfm testWade Fife2020-03-095-5/+675
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* examples: Update gain block testbench to use samplesWade Fife2020-03-092-26/+25
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* sim: Add item support to RFNoC simulationWade Fife2020-03-098-40/+420
| | | | | This adds variants of the send and recv methods in RfnocBlockCtrlBfm and ChdrIfaceBfm that input/output items instead of CHDR words.
* sim: Parameterize chdr_word_t data typeWade Fife2020-03-0918-218/+423
| | | | | | | | | | | | | | | | | | This replaces chdr_word_t, which was a statically defined 64-bit data type, with a paramaterizable data type that matches the defined CHDR_W. Code that formerly referenced the chdr_word_t data type can now define the data type for their desired CHDR_W and ITEM_W as follows: // Define the CHDR word and item/sample data types typedef ChdrData #(CHDR_W, ITEM_W)::chdr_word_t chdr_word_t; typedef ChdrData #(CHDR_W, ITEM_W)::item_t item_t; ITEM_W is optional when defining chdr_word_t if items are not needed. Static methods in the ChdrData class also provide the ability to convert between CHDR words and data items. For example: // Convert CHDR data buffer to a buffer of samples samples = ChdrData#(CHDR_W, ITEM_W)::chdr_to_item(data);
* sim: Split PkgRfnocBlockCtrlBfm into separate packagesWade Fife2020-03-095-400/+418
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* fpga: lib: Modify for loop to Verilog 2001 syntaxMax Köhler2020-03-091-34/+35
| | | | | | This changes the for loop to use the generate keyword, making it compatible with Verilog 2001. This allows tools that only support Verilog 2001 to use this file (e.g., Intel Quartus).
* rfnoc: Fix FIR and AXI RAM block register documentationWade Fife2020-03-052-9/+11
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* mpm: rpc_server: set correct default unpacker params for msgpack 0.6.1Joerg Hofrichter2020-03-051-2/+2
| | | | | | | | | | | | | | | | | | | | | | msgpack 0.6.1 suggests new default parameters which ensures compatibility with the upcoming msgpack 1.0 release which will have breaking changes. The parameter changes are described in https://github.com/msgpack/msgpack-python/blob/v0.6.1/README.rst The default parameters for msgpack 1.0 will be: - packer: use_bin_type=True - unpacker: raw=False The packer use_bin_type=True option is already set in the client (mpm_shell.py) but the unpacker option raw=False needs to be set in the server (rpc_server.py) This change allows the usage of a patched version of python3-mprpc 0.1.17 which removes passing the encoding option to the Packer and Unpacker Signed-off-by: Joerg Hofrichter <joerg.hofrichter@ni.com>
* mpm: explicitly set max buffer size for msgpack unpackerAndrew Lynch2020-03-051-0/+2
| | | | | | Msgpack version 0.6 reduced the default max buffer size to 1MB which is smaller than the bitfiles. This change sets the max buffer size to 50MB which is larger than the bitfiles.
* Add TwinRX support to phase alignment scripterickshepherdNI2020-03-051-19/+57
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* mpm: Make contextmanagers exception-safeLane Kolbly2020-03-034-5/+68
| | | | When making context managers in Python, the yield statement has to be wrapped in a try/finally clause in order to properly clean up after exceptions happen.
* mpm: rpc: Use contextmanager for claim timeoutsToni Jones2020-03-031-33/+38
| | | | | Modify the RPC claim timeout mechanism to use a contextmanager helper function when enabling/disabling timeouts.
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