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* uhd: cal: Add iq_cal calibration data container classMartin Braun2020-04-0217-1/+760
* uhd: Add calibration container classMartin Braun2020-04-023-0/+68
* fpga: tools: Add support for .sdc in VivadoPaul Butler2020-04-021-0/+3
* fpga: rfnoc: Add gate to dynamically enable control-port interfacesMax Köhler2020-04-011-0/+91
* fpga: rfnoc: ctrport_combiner with deterministic latency for PRIORITY=1Max Köhler2020-04-011-13/+51
* fpga: tools: Add default Vivado install locationWade Fife2020-04-011-1/+5
* multi_usrp: Fix ALL_CHAN and ALL_MBOARDS API calls for Gen-3 devicesMartin Braun2020-03-311-105/+64
* utils: uhd_usrp_probe: Output frontend infoMichael West2020-03-311-5/+13
* docs: Update Basic/LF dboard references to use new operating modemattprost2020-03-312-21/+31
* examples: Change benchmark_rate default thread priorityAaron Rossetto2020-03-271-1/+1
* fixup! x300: lf/basic antenna API implementationMartin Braun2020-03-261-2/+2
* uhd: cal: Add database classMartin Braun2020-03-2612-0/+542
* uhd: paths: Add get_cal_data_path() API callMartin Braun2020-03-263-1/+25
* fpga: tools: Add ModelSim to run_testbenches.pyWade Fife2020-03-231-11/+11
* fixup! fpga: tools: Add modelsim to make sim targetsWade Fife2020-03-231-27/+25
* x300: lf/basic antenna API implementationmattprost2020-03-234-110/+234
* fpga: Fix errors found by linting with vsimAndrew Moch2020-03-236-19/+22
* utils: uhd_images_downloader: use HTTPS instead of HTTP to avoid redirectMarcus Müller2020-03-201-1/+1
* fpga: tools: Add modelsim to make sim targetsAndrew Moch2020-03-204-35/+127
* uhd: math: Add linear_interp()Martin Braun2020-03-182-7/+30
* debian: Rename control file for libuhd to contain 4.0.0 versionMartin Braun2020-03-181-0/+0
* debian: Fixes to copyright fileMartin Braun2020-03-181-389/+385
* cmake: Add CMakeRC module and ::rc namespaceMartin Braun2020-03-184-1/+665
* lib: deps: Add FlatBuffers 1.11.0 header filesMartin Braun2020-03-1817-0/+9179
* lib: Use from_str<bool> in constrained_device_args_tAaron Rossetto2020-03-181-17/+7
* utils: Add bool specialization to cast::from_str()Aaron Rossetto2020-03-183-0/+60
* tests: Allow custom name for mock terminatorAaron Rossetto2020-03-131-4/+6
* tests: Allow custom mock_reg_iface_t in mock blockAaron Rossetto2020-03-132-8/+10
* fpga: tools: Ignore BD layout info for TCL-based BDHumberto Jimenez2020-03-121-1/+1
* utils: cal: Replace property tree accesses with other API callsMartin Braun2020-03-121-43/+35
* multi_usrp: Provide valid return value for multi_usrp::get_device()Martin Braun2020-03-123-8/+72
* utils/C API: Fix property tree accessMartin Braun2020-03-123-8/+8
* python: Export UHD paths utility functionsMartin Braun2020-03-123-0/+30
* python: Remove Python2-specific codeMartin Braun2020-03-121-7/+0
* lib: gain_group: Remove spurious logsMartin Braun2020-03-121-2/+0
* python: Arrange file in Python module into uhd/ subdirectoryMartin Braun2020-03-108-21/+54
* README.md: Update references to fpga-srcLane Kolbly2020-03-101-10/+2
* sim: Rename class typedefsWade Fife2020-03-094-72/+72
* sim: Add ChdrIfaceBfm testWade Fife2020-03-095-5/+675
* examples: Update gain block testbench to use samplesWade Fife2020-03-092-26/+25
* sim: Add item support to RFNoC simulationWade Fife2020-03-098-40/+420
* sim: Parameterize chdr_word_t data typeWade Fife2020-03-0918-218/+423
* sim: Split PkgRfnocBlockCtrlBfm into separate packagesWade Fife2020-03-095-400/+418
* fpga: lib: Modify for loop to Verilog 2001 syntaxMax Köhler2020-03-091-34/+35
* rfnoc: Fix FIR and AXI RAM block register documentationWade Fife2020-03-052-9/+11
* mpm: rpc_server: set correct default unpacker params for msgpack 0.6.1Joerg Hofrichter2020-03-051-2/+2
* mpm: explicitly set max buffer size for msgpack unpackerAndrew Lynch2020-03-051-0/+2
* Add TwinRX support to phase alignment scripterickshepherdNI2020-03-051-19/+57
* mpm: Make contextmanagers exception-safeLane Kolbly2020-03-034-5/+68
* mpm: rpc: Use contextmanager for claim timeoutsToni Jones2020-03-031-33/+38
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