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| | * | | | | | | | | | left something out of the sensitivity list.Matt Ettus2010-06-101-1/+1
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| | * | | | | | | | | | proper overrun, underrun connections, debug pins.Matt Ettus2010-06-101-4/+8
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| | * | | | | | | | | | ignoresMatt Ettus2010-06-081-0/+1
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| | * | | | | | | | | | debug pinsMatt Ettus2010-06-083-4/+10
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| | * | | | | | | | | | Merge branch 'master' into u1eMatt Ettus2010-06-083-15/+17
| | |\ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * master: allow other clock rates in vita time report ise version in build proper name for directory name build directory with ISE version name
| | * | | | | | | | | | | remove double declarationMatt Ettus2010-06-061-1/+1
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| | * | | | | | | | | | | use fifo19 not fifo18 in makefileMatt Ettus2010-06-061-1/+1
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| | * | | | | | | | | | | added little endian capability for gpmc to fifo and fifo to gpmc, since ARM ↵Matt Ettus2010-06-064-41/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | is LE.
| | * | | | | | | | | | | get rid of redundant fifo18, since we can just use fifo19 and ignore the occ bitMatt Ettus2010-06-063-44/+6
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| | * | | | | | | | | | | Phil wants gpio #145Matt Ettus2010-06-032-4/+4
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| | * | | | | | | | | | | use same version as usrp2-udp, so regs are same place in memory mapMatt Ettus2010-06-012-2/+2
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| | * | | | | | | | | | | Merge branch 'ise12_exp' into u1eMatt Ettus2010-06-0111-391/+1749
| | |\ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * ise12_exp: zero out debug pins. helps timing a little bit. non-udp uses a different address for the tx dsp core manual merge to use localparams from udp version from UDP branch, changed names because I want these separate from the non-udp versions ignore output files new files from udp branch added to main Makefile change the debug pins, which makes it more reliable. This is unnerving. experimental mods to make ram loader fully synchronous. Based on IJB's work fixes from IJB from 5/24. Basically connect unconnected wires. removes the icache and pipelines the reads
| | | * | | | | | | | | | | zero out debug pins. helps timing a little bit.Matt Ettus2010-06-011-9/+11
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| | | * | | | | | | | | | | Merge branch 'new_ramloader' into nocache_plus_newramloader, plus manual ↵Matt Ettus2010-05-284-250/+280
| | | |\ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | merge into udp version. Raw ethernet, ISE 10 -- Passes timing, works UDP, ISE 10 -- barely fails timing, works ISE 12 -- both fail timing, not tested yet. * new_ramloader: experimental mods to make ram loader fully synchronous. Based on IJB's work
| | | | * | | | | | | | | | | experimental mods to make ram loader fully synchronous. Based on IJB's workMatt Ettus2010-05-263-235/+266
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| | | * | | | | | | | | | | | Merge branch 'master_nocache' into master_nocache_post_mergeMatt Ettus2010-05-287-26/+114
| | | |\ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Seems to work on raw ethernet version which was automatically merged UDP version untested, and the following files were merged manually: u2_core_udp.v Makefile.udp * master_nocache: change the debug pins, which makes it more reliable. This is unnerving. fixes from IJB from 5/24. Basically connect unconnected wires. removes the icache and pipelines the reads
| | | | * | | | | | | | | | | | change the debug pins, which makes it more reliable. This is unnerving.Matt Ettus2010-05-261-1/+2
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| | | | * | | | | | | | | | | fixes from IJB from 5/24. Basically connect unconnected wires.Matt Ettus2010-05-242-2/+5
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| | | | * | | | | | | | | | | removes the icache and pipelines the readsMatt Ettus2010-05-205-16/+98
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| | * | | | | | | | | | | | | connect the rx run lines so it doesn't get optimized outMatt Ettus2010-06-011-1/+4
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| | * | | | | | | | | | | | | use DDR regs instead of a 2nd clockMatt Ettus2010-06-011-8/+46
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| | * | | | | | | | | | | | | assign addresses for the settings regsMatt Ettus2010-06-011-5/+6
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| | * | | | | | | | | | | | | vita49 tx and rx added in, all sample rates now at main system clock rate.Matt Ettus2010-06-014-107/+220
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| | * | | | | | | | | | | | | Merge branch 'udp' into u1e_merge_with_udpMatt Ettus2010-05-274-172/+72
| | |\ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * udp: better test program for just the tx side fix typo, no functionality difference ignores move dsp settings regs to reclocked setting bus. Works, gets us to within 18ps of passing timing reverting logic clean up which should have made timing better, but made it worse instead Conflicts: usrp2/control_lib/settings_bus.v usrp2/top/u2_core/u2_core.v
| | * \ \ \ \ \ \ \ \ \ \ \ \ \ Merge branch 'master' into u1e_merge_with_masterMatt Ettus2010-05-27235-2409/+30
| | |\ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | |_|/ / / / / / / / / / / | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * master: get rid of some warnings by declaring setting reg width added width parameter to avoid warnings (thanks IJB) and default value parameter added pragmas suggested by Ian Buckley to help ISE12 synthesis get rid of old CVS linkage settings bus to dsp_clk now uses clock crossing fifo remove files for old prototypes, they were confusing people revert commit 9899b81f920 which should have improved timing but didn't Conflicts: usrp2/control_lib/setting_reg.v usrp2/top/u2_core/u2_core.v usrp2/top/u2_rev3/Makefile
| | * | | | | | | | | | | | | | test full width packetsMatt Ettus2010-05-241-0/+27
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| | * | | | | | | | | | | | | | fifo36_to_ll8 and fifo pacer need a real fifo between them or they deadlock ↵Matt Ettus2010-05-211-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | (by design)
| | * | | | | | | | | | | | | | fix double declarationMatt Ettus2010-05-211-1/+0
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| | * | | | | | | | | | | | | | send bigger packets to reduce cpu loadMatt Ettus2010-05-202-3/+3
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| | * | | | | | | | | | | | | | put over/underrun on debug bus, remove high order address bitsMatt Ettus2010-05-201-1/+2
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| | * | | | | | | | | | | | | | Merge branch 'u1e' of ettus.sourcerepo.com:ettus/fpgapriv into u1eMatt Ettus2010-05-201-4/+2
| | |\ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: usrp2/top/u1e/u1e_core.v
| | | * | | | | | | | | | | | | | better debug pinsMatt Ettus2010-05-171-6/+4
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| | * | | | | | | | | | | | | | | combined timed and crc cases. fifo pacer produces/consumes at a fixed rateMatt Ettus2010-05-203-34/+48
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| | * | | | | | | | | | | | | | moved fifos into gpmc_async, reorganized top level a bit, added in crc ↵Matt Ettus2010-05-126-66/+144
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| | * | | | | | | | | | | | | | add missing signal from sensitivity listMatt Ettus2010-05-121-1/+1
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| | * | | | | | | | | | | | | | Merge branch 'master' into u1eMatt Ettus2010-05-1217-46/+587
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| | * | | | | | | | | | | | | | | packet generator and verifier, to test gpmc and other data transfer stuffMatt Ettus2010-05-124-0/+153
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| | * | | | | | | | | | | | | | | switched passthru of cgen_sen_b to gpio127, made a note of it. No more ↵Matt Ettus2010-05-108-561/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | safe_u1e necessary.
| | * | | | | | | | | | | | | | | proper signal level for 24 bit dataMatt Ettus2010-05-101-2/+7
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| | * | | | | | | | | | | | | | | SPI passthru for programming clock gen chip on brand new boardsMatt Ettus2010-05-073-0/+391
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| | * | | | | | | | | | | | | | | added DAC output pins, and a sine wave generator to test themMatt Ettus2010-05-043-18/+63
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| | * | | | | | | | | | | | | | | Merge branch 'u1e' of ettus.sourcerepo.com:ettus/fpgapriv into u1eMatt Ettus2010-05-042-0/+14
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| | | * | | | | | | | | | | | | | | add timing constraints. Just have main clock signal at 64 MHz for now.Matt Ettus2010-05-042-0/+14
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| | * | | | | | | | | | | | | | | | changed commentMatt Ettus2010-05-041-1/+1
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| | * | | | | | | | | | | | | | | have_space and have_packet now stay high even while busy,Matt Ettus2010-05-033-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | as long as there really is more data/space. This should allow bursting without having additional interrupts. Also lenghten RX FIFO
| | * | | | | | | | | | | | | | | separate timed tx and rx instead of loopbackMatt Ettus2010-04-281-3/+51
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| | * | | | | | | | | | | | | | | send bus error to debug pinsMatt Ettus2010-04-261-2/+4
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| | * | | | | | | | | | | | | | | Pass previously unused GPIOs to debug pins to help debug interruptsMatt Ettus2010-04-243-16/+21
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| | * | | | | | | | | | | | | | | Only allow new packets if we can fit the largest possible packet (2KB)Matt Ettus2010-04-231-1/+1
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| | * | | | | | | | | | | | | | | Register outputs to omap to prevent runt pulses from falsely triggering ↵Matt Ettus2010-04-233-7/+20
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generated by cgit v1.2.3 (git 2.39.1) at 2024-11-15 15:31:15 +0000