| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | | * | | | | | | | | | | | | | | | find time_64bit | Matt Ettus | 2010-04-20 | 1 | -0/+1 | |
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| | | * | | | | | | | | | | | | | | | added pps and time capability | Matt Ettus | 2010-04-15 | 3 | -5/+21 | |
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| | | * | | | | | | | | | | | | | | | access frame length regs from wishbone | Matt Ettus | 2010-04-15 | 2 | -10/+18 | |
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| | | * | | | | | | | | | | | | | | | async seems to work with packet lengths now. Still need to do wishbone regs ↵ | Matt Ettus | 2010-04-15 | 5 | -37/+72 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | for gpmc | |||||
| | | * | | | | | | | | | | | | | | | async gpmc progress | Matt Ettus | 2010-04-15 | 4 | -18/+173 | |
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| | | * | | | | | | | | | | | | | | | change time parameters because Xilinx IP has a 1ps timescale | Matt Ettus | 2010-04-15 | 1 | -14/+27 | |
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| | | * | | | | | | | | | | | | | | | add bus error reporting | Matt Ettus | 2010-04-15 | 1 | -3/+9 | |
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| | | * | | | | | | | | | | | | | | | correct name of module | Matt Ettus | 2010-04-15 | 1 | -2/+2 | |
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| | | * | | | | | | | | | | | | | | | progress on synchronous gpmc, but it may not be possible due to the limited ↵ | Matt Ettus | 2010-04-15 | 3 | -43/+45 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | number of clock edges | |||||
| | | * | | | | | | | | | | | | | | | synchronous and asynchronous gpmc models | Matt Ettus | 2010-04-15 | 3 | -3/+100 | |
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| | | * | | | | | | | | | | | | | | | handle all tri-state in the top level of gpmc | Matt Ettus | 2010-04-15 | 3 | -6/+8 | |
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| | | * | | | | | | | | | | | | | | | more sync progress. This is just a skeleton for now, with junk content | Matt Ettus | 2010-04-14 | 1 | -0/+56 | |
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| | | * | | | | | | | | | | | | | | | more progress on synchronous interface | Matt Ettus | 2010-04-14 | 4 | -26/+95 | |
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| | | * | | | | | | | | | | | | | | | renamed to async. Will be building a sync version for GPMC_CLK | Matt Ettus | 2010-04-14 | 2 | -3/+3 | |
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| | | * | | | | | | | | | | | | | | | make timing diagrams for bus transactions. Still need to do reads | Matt Ettus | 2010-04-14 | 5 | -0/+46 | |
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| | | * | | | | | | | | | | | | | | | added in a loopback fifo | Matt Ettus | 2010-04-14 | 1 | -4/+11 | |
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| | | * | | | | | | | | | | | | | | | probably won't be using this, and it hasn't been tested | Matt Ettus | 2010-04-14 | 1 | -0/+46 | |
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| | | * | | | | | | | | | | | | | | | minor changes to get it to synthesize | Matt Ettus | 2010-04-13 | 2 | -1/+4 | |
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| | | * | | | | | | | | | | | | | | | lengthened delay between cycles, added more transactions on the data bus | Matt Ettus | 2010-04-12 | 1 | -2/+7 | |
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| | | * | | | | | | | | | | | | | | | replaced ram interface with a fifo interface. still need to do rx side | Matt Ettus | 2010-04-12 | 3 | -120/+117 | |
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| | | * | | | | | | | | | | | | | | | split out gpmc to wishbone interface to make gpmc top level cleaner | Matt Ettus | 2010-04-12 | 1 | -0/+57 | |
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| | | * | | | | | | | | | | | | | | | added 16-bit wide atr controller | Matt Ettus | 2010-04-01 | 5 | -47/+117 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | settings_bus_16 now handles variable address window sizes split ctrl of nsgpio into ctrl (selector) and debug bits | |||||
| | | * | | | | | | | | | | | | | | | 16 bit wide spi core | Matt Ettus | 2010-03-27 | 1 | -0/+182 | |
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| | | * | | | | | | | | | | | | | | | connect up the 16 bit spi core | Matt Ettus | 2010-03-26 | 2 | -5/+4 | |
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| | | * | | | | | | | | | | | | | | | remove timescale junk | Matt Ettus | 2010-03-26 | 5 | -21/+19 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | get rid of asynchronous resets fix spelling error corrected comment | |||||
| | | * | | | | | | | | | | | | | | | connect 2 clock gen controls and 3 status pins to the wishbone so they can ↵ | Matt Ettus | 2010-03-26 | 3 | -8/+26 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | be read/controlled from SW | |||||
| | | * | | | | | | | | | | | | | | | Merge branch 'udp' into u1e | Matt Ettus | 2010-03-25 | 32 | -132/+2545 | |
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| | | * | | | | | | | | | | | | | | | | connected spi pins, but the spi core still needs to be redone for 16 bit ↵ | Matt Ettus | 2010-03-25 | 3 | -40/+60 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | interfaces Also reconnected GPIOs so you'll need to send commands in order to get debug pins on the GPIOs | |||||
| | | * | | | | | | | | | | | | | | | | debug pins | Matt Ettus | 2010-02-25 | 1 | -2/+3 | |
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| | | * | | | | | | | | | | | | | | | | enable was on the wrong address pin, needs to be the highest order one | Matt Ettus | 2010-02-25 | 1 | -2/+2 | |
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| | | * | | | | | | | | | | | | | | | | invert the pushbuttons since they are active low | Matt Ettus | 2010-02-25 | 1 | -2/+2 | |
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| | | * | | | | | | | | | | | | | | | | gpmc debug pins | Matt Ettus | 2010-02-25 | 2 | -4/+14 | |
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| | | * | | | | | | | | | | | | | | | | point to the new files | Matt Ettus | 2010-02-25 | 1 | -0/+2 | |
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| | | * | | | | | | | | | | | | | | | | fix syntax error which icarus allowed (filed a bug with them) | Matt Ettus | 2010-02-25 | 1 | -7/+9 | |
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| | | * | | | | | | | | | | | | | | | | loopback and test | Matt Ettus | 2010-02-25 | 2 | -7/+38 | |
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| | | * | | | | | | | | | | | | | | | | corrected logic | Matt Ettus | 2010-02-25 | 1 | -17/+7 | |
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| | | * | | | | | | | | | | | | | | | | edge sync on done signals so we only fill/empty one buffer | Matt Ettus | 2010-02-25 | 2 | -2/+32 | |
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| | | * | | | | | | | | | | | | | | | | Switched xilinx primitives because they order the bits funny in the other one | Matt Ettus | 2010-02-25 | 1 | -48/+79 | |
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| | | * | | | | | | | | | | | | | | | | ISE chokes on the pure verilog version so we use the macro | Matt Ettus | 2010-02-25 | 1 | -4/+49 | |
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| | | * | | | | | | | | | | | | | | | | First cut at passing data buffers around on GPMC bus | Matt Ettus | 2010-02-25 | 6 | -25/+165 | |
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| | | * | | | | | | | | | | | | | | | | Merge branch 'master' into u1e | Matt Ettus | 2010-02-23 | 2 | -1/+3 | |
| | | |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: .gitignore | |||||
| | | * | | | | | | | | | | | | | | | | | first cut at making a bidirectional 2 port ram for the gpmc data interface | Matt Ettus | 2010-02-23 | 3 | -6/+63 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ISE chokes on the unequal size ram | |||||
| | | * | | | | | | | | | | | | | | | | | use our fancy new debug ports | Matt Ettus | 2010-02-23 | 1 | -0/+3 | |
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| | | * | | | | | | | | | | | | | | | | | settings bus with 16 bit wishbone interface, put on the main wishbone in u1e | Matt Ettus | 2010-02-22 | 3 | -3/+68 | |
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| | | * | | | | | | | | | | | | | | | | | remove the #1 delay in all the regs. They just slow down sims. | Matt Ettus | 2010-02-22 | 4 | -96/+90 | |
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| | | * | | | | | | | | | | | | | | | | | Modified nsgpio.v to support 16 bit little endian bus interface. | Matt Ettus | 2010-02-22 | 1 | -0/+124 | |
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| | | * | | | | | | | | | | | | | | | | | GPIOs now on the wishbone interface | Matt Ettus | 2010-02-22 | 4 | -37/+54 | |
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| | | * | | | | | | | | | | | | | | | | | added gpio control to the wishbone | Matt Ettus | 2010-02-18 | 2 | -11/+14 | |
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| | | * | | | | | | | | | | | | | | | | | Added I2C, UART, debug pins, misc wishbone stuff | Matt Ettus | 2010-02-18 | 3 | -48/+187 | |
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| | | * | | | | | | | | | | | | | | | | | allow default uart clock divider | Matt Ettus | 2010-02-18 | 1 | -6/+7 | |
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