remove timescale junk

get rid of asynchronous resets

fix spelling error

corrected comment

5 files changed, 19 insertions, 21 deletions

diff --git a/usrp2/opencores/spi/rtl/verilog/spi_clgen.v b/usrp2/opencores/spi/rtl/verilog/spi_clgen.v
index 3f29f6d7f..2d9c34f40 100644
--- a/usrp2/opencores/spi/rtl/verilog/spi_clgen.v
+++ b/usrp2/opencores/spi/rtl/verilog/spi_clgen.v
@@ -39,7 +39,6 @@
 //////////////////////////////////////////////////////////////////////
 
 `include "spi_defines.v"
-`include "timescale.v"
 
 module spi_clgen (clk_in, rst, go, enable, last_clk, divider, clk_out, pos_edge, neg_edge); 
 
@@ -66,7 +65,7 @@ module spi_clgen (clk_in, rst, go, enable, last_clk, divider, clk_out, pos_edge,
   assign cnt_one  = cnt == {{`SPI_DIVIDER_LEN-1{1'b0}}, 1'b1};
   
   // Counter counts half period
-  always @(posedge clk_in or posedge rst)
+  always @(posedge clk_in)
   begin
     if(rst)
       cnt <= {`SPI_DIVIDER_LEN{1'b1}};
@@ -80,7 +79,7 @@ module spi_clgen (clk_in, rst, go, enable, last_clk, divider, clk_out, pos_edge,
   end
   
   // clk_out is asserted every other half period
-  always @(posedge clk_in or posedge rst)
+  always @(posedge clk_in)
   begin
     if(rst)
       clk_out <= 1'b0;
@@ -89,7 +88,7 @@ module spi_clgen (clk_in, rst, go, enable, last_clk, divider, clk_out, pos_edge,
   end
    
   // Pos and neg edge signals
-  always @(posedge clk_in or posedge rst)
+  always @(posedge clk_in)
   begin
     if(rst)
       begin
diff --git a/usrp2/opencores/spi/rtl/verilog/spi_defines.v b/usrp2/opencores/spi/rtl/verilog/spi_defines.v
index 01de2584d..963a680a8 100644
--- a/usrp2/opencores/spi/rtl/verilog/spi_defines.v
+++ b/usrp2/opencores/spi/rtl/verilog/spi_defines.v
@@ -137,7 +137,7 @@
 `define SPI_TX_2                2
 `define SPI_TX_3                3
 `define SPI_CTRL                4
-`define SPI_DEVIDE              5
+`define SPI_DIVIDE              5
 `define SPI_SS                  6
 
 //
diff --git a/usrp2/opencores/spi/rtl/verilog/spi_shift.v b/usrp2/opencores/spi/rtl/verilog/spi_shift.v
index c8c73706b..ac3bb3f48 100644
--- a/usrp2/opencores/spi/rtl/verilog/spi_shift.v
+++ b/usrp2/opencores/spi/rtl/verilog/spi_shift.v
@@ -39,7 +39,6 @@
 //////////////////////////////////////////////////////////////////////
 
 `include "spi_defines.v"
-`include "timescale.v"
 
 module spi_shift (clk, rst, latch, byte_sel, len, lsb, go,
                   pos_edge, neg_edge, rx_negedge, tx_negedge,
@@ -87,7 +86,7 @@ module spi_shift (clk, rst, latch, byte_sel, len, lsb, go,
   assign tx_clk = (tx_negedge ? neg_edge : pos_edge) && !last;
   
   // Character bit counter
-  always @(posedge clk or posedge rst)
+  always @(posedge clk)
   begin
     if(rst)
       cnt <= {`SPI_CHAR_LEN_BITS+1{1'b0}};
@@ -101,7 +100,7 @@ module spi_shift (clk, rst, latch, byte_sel, len, lsb, go,
   end
   
   // Transfer in progress
-  always @(posedge clk or posedge rst)
+  always @(posedge clk)
   begin
     if(rst)
       tip <= 1'b0;
@@ -112,7 +111,7 @@ module spi_shift (clk, rst, latch, byte_sel, len, lsb, go,
   end
   
   // Sending bits to the line
-  always @(posedge clk or posedge rst)
+  always @(posedge clk)
   begin
     if (rst)
       s_out   <= 1'b0;
@@ -121,7 +120,7 @@ module spi_shift (clk, rst, latch, byte_sel, len, lsb, go,
   end
   
   // Receiving bits from the line
-  always @(posedge clk or posedge rst)
+  always @(posedge clk)
   begin
     if (rst)
       data   <= {`SPI_MAX_CHAR{1'b0}};
diff --git a/usrp2/opencores/spi/rtl/verilog/spi_top.v b/usrp2/opencores/spi/rtl/verilog/spi_top.v
index 071aeefca..8289449a9 100644
--- a/usrp2/opencores/spi/rtl/verilog/spi_top.v
+++ b/usrp2/opencores/spi/rtl/verilog/spi_top.v
@@ -1,3 +1,6 @@
+
+// Modified 2010 by Matt Ettus to remove old verilog style
+
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
 ////  spi_top.v                                                   ////
@@ -40,7 +43,6 @@
 
 
 `include "spi_defines.v"
-`include "timescale.v"
 
 module spi_top
 (
@@ -99,7 +101,7 @@ module spi_top
   wire                             last_bit;         // marks last character bit
   
   // Address decoder
-  assign spi_divider_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_DEVIDE);
+  assign spi_divider_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_DIVIDE);
   assign spi_ctrl_sel    = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_CTRL);
   assign spi_tx_sel[0]   = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_0);
   assign spi_tx_sel[1]   = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_1);
@@ -130,14 +132,14 @@ module spi_top
 `endif
 `endif
       `SPI_CTRL:    wb_dat = {{32-`SPI_CTRL_BIT_NB{1'b0}}, ctrl};
-      `SPI_DEVIDE:  wb_dat = {{32-`SPI_DIVIDER_LEN{1'b0}}, divider};
+      `SPI_DIVIDE:  wb_dat = {{32-`SPI_DIVIDER_LEN{1'b0}}, divider};
       `SPI_SS:      wb_dat = {{32-`SPI_SS_NB{1'b0}}, ss};
       default:      wb_dat = 32'bx;
     endcase
   end
   
   // Wb data out
-  always @(posedge wb_clk_i or posedge wb_rst_i)
+  always @(posedge wb_clk_i)
   begin
     if (wb_rst_i)
       wb_dat_o <= 32'b0;
@@ -146,7 +148,7 @@ module spi_top
   end
   
   // Wb acknowledge
-  always @(posedge wb_clk_i or posedge wb_rst_i)
+  always @(posedge wb_clk_i)
   begin
     if (wb_rst_i)
       wb_ack_o <= 1'b0;
@@ -158,7 +160,7 @@ module spi_top
   assign wb_err_o = 1'b0;
   
   // Interrupt
-  always @(posedge wb_clk_i or posedge wb_rst_i)
+  always @(posedge wb_clk_i)
   begin
     if (wb_rst_i)
       wb_int_o <= 1'b0;
@@ -169,7 +171,7 @@ module spi_top
   end
   
   // Divider register
-  always @(posedge wb_clk_i or posedge wb_rst_i)
+  always @(posedge wb_clk_i)
   begin
     if (wb_rst_i)
         divider <= {`SPI_DIVIDER_LEN{1'b0}};
@@ -207,7 +209,7 @@ module spi_top
   end
   
   // Ctrl register
-  always @(posedge wb_clk_i or posedge wb_rst_i)
+  always @(posedge wb_clk_i)
   begin
     if (wb_rst_i)
       ctrl <= {`SPI_CTRL_BIT_NB{1'b0}};
@@ -231,7 +233,7 @@ module spi_top
   assign ass        = ctrl[`SPI_CTRL_ASS];
   
   // Slave select register
-  always @(posedge wb_clk_i or posedge wb_rst_i)
+  always @(posedge wb_clk_i)
   begin
     if (wb_rst_i)
       ss <= {`SPI_SS_NB{1'b0}};
diff --git a/usrp2/opencores/spi/rtl/verilog/timescale.v b/usrp2/opencores/spi/rtl/verilog/timescale.v
deleted file mode 100644
index 60d4ecbd1..000000000
--- a/usrp2/opencores/spi/rtl/verilog/timescale.v
+++ /dev/null
@@ -1,2 +0,0 @@
-`timescale 1ns / 10ps
-