diff options
Diffstat (limited to 'usrp2/vrt')
| -rw-r--r-- | usrp2/vrt/vita_rx_engine_glue.v | 4 | ||||
| -rw-r--r-- | usrp2/vrt/vita_tx_engine_glue.v | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/usrp2/vrt/vita_rx_engine_glue.v b/usrp2/vrt/vita_rx_engine_glue.v index 86e3d1114..56447a7aa 100644 --- a/usrp2/vrt/vita_rx_engine_glue.v +++ b/usrp2/vrt/vita_rx_engine_glue.v @@ -65,7 +65,7 @@ module vita_rx_engine_glue .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), .access_dat_i(access_dat_i), .access_dat_o(access_dat_o)); `else - RX_ENG0_MODULE #(.BUF_SIZE(BUF_SIZE)) rx_eng0_custom + `RX_ENG0_MODULE #(.BUF_SIZE(BUF_SIZE)) rx_eng0_custom (.clock(clock),.reset(reset),.clear(clear), .set_stb(set_stb_user), .set_addr(set_addr_user), .set_data(set_data_user), .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), @@ -82,7 +82,7 @@ module vita_rx_engine_glue .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), .access_dat_i(access_dat_i), .access_dat_o(access_dat_o)); `else - RX_ENG1_MODULE #(.BUF_SIZE(BUF_SIZE)) rx_eng1_custom + `RX_ENG1_MODULE #(.BUF_SIZE(BUF_SIZE)) rx_eng1_custom (.clock(clock),.reset(reset),.clear(clear), .set_stb(set_stb_user), .set_addr(set_addr_user), .set_data(set_data_user), .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), diff --git a/usrp2/vrt/vita_tx_engine_glue.v b/usrp2/vrt/vita_tx_engine_glue.v index b0a81c3e9..db0d55dee 100644 --- a/usrp2/vrt/vita_tx_engine_glue.v +++ b/usrp2/vrt/vita_tx_engine_glue.v @@ -69,7 +69,7 @@ module vita_tx_engine_glue .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), .access_dat_i(access_dat_i), .access_dat_o(access_dat_o)); `else - TX_ENG0_MODULE #(.BUF_SIZE(BUF_SIZE), .HEADER_OFFSET(HEADER_OFFSET)) tx_eng0_custom + `TX_ENG0_MODULE #(.BUF_SIZE(BUF_SIZE), .HEADER_OFFSET(HEADER_OFFSET)) tx_eng0_custom (.clock(clock),.reset(reset),.clear(clear), .set_stb(set_stb_user), .set_addr(set_addr_user), .set_data(set_data_user), .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), @@ -86,7 +86,7 @@ module vita_tx_engine_glue .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), .access_dat_i(access_dat_i), .access_dat_o(access_dat_o)); `else - TX_ENG1_MODULE #(.BUF_SIZE(BUF_SIZE), .HEADER_OFFSET(HEADER_OFFSET)) tx_eng1_custom + `TX_ENG1_MODULE #(.BUF_SIZE(BUF_SIZE), .HEADER_OFFSET(HEADER_OFFSET)) tx_eng1_custom (.clock(clock),.reset(reset),.clear(clear), .set_stb(set_stb_user), .set_addr(set_addr_user), .set_data(set_data_user), .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), |