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-rw-r--r--usrp2/top/B100/u1plus_core.v9
-rw-r--r--usrp2/top/E1x0/u1e_core.v7
-rw-r--r--usrp2/top/N2x0/u2plus_core.v8
-rw-r--r--usrp2/top/USRP2/u2_core.v8
4 files changed, 21 insertions, 11 deletions
diff --git a/usrp2/top/B100/u1plus_core.v b/usrp2/top/B100/u1plus_core.v
index 1981123bc..4c3acaa27 100644
--- a/usrp2/top/B100/u1plus_core.v
+++ b/usrp2/top/B100/u1plus_core.v
@@ -169,9 +169,10 @@ module u1plus_core
.sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0),
.debug() );
- vita_rx_chain #(.BASE(SR_RX_CTRL0), .UNIT(0), .FIFOSIZE(10), .PROT_ENG_FLAGS(0)) vita_rx_chain0
+ vita_rx_chain #(.BASE(SR_RX_CTRL0), .UNIT(0), .FIFOSIZE(10), .PROT_ENG_FLAGS(0), .DSP_NUMBER(0)) vita_rx_chain0
(.clk(wb_clk),.reset(wb_rst),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+ .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
.vita_time(vita_time), .overrun(rx_overrun_dsp0),
.sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0),
.rx_data_o(vita_rx_data0), .rx_dst_rdy_i(vita_rx_dst_rdy0), .rx_src_rdy_o(vita_rx_src_rdy0),
@@ -193,9 +194,10 @@ module u1plus_core
.sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1),
.debug() );
- vita_rx_chain #(.BASE(SR_RX_CTRL1), .UNIT(1), .FIFOSIZE(10), .PROT_ENG_FLAGS(0)) vita_rx_chain1
+ vita_rx_chain #(.BASE(SR_RX_CTRL1), .UNIT(1), .FIFOSIZE(10), .PROT_ENG_FLAGS(0), .DSP_NUMBER(1)) vita_rx_chain1
(.clk(wb_clk),.reset(wb_rst),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+ .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
.vita_time(vita_time), .overrun(rx_overrun_dsp1),
.sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1),
.rx_data_o(vita_rx_data1), .rx_dst_rdy_i(vita_rx_dst_rdy1), .rx_src_rdy_o(vita_rx_src_rdy1),
@@ -218,13 +220,14 @@ module u1plus_core
wire [31:0] sample_tx;
wire strobe_tx;
- vita_tx_chain #(.BASE(SR_TX_CTRL), .FIFOSIZE(10),
+ vita_tx_chain #(.BASE(SR_TX_CTRL), .FIFOSIZE(0/*no engine*/),
.REPORT_ERROR(1), .DO_FLOW_CONTROL(0),
.PROT_ENG_FLAGS(0), .USE_TRANS_HEADER(0),
.DSP_NUMBER(0))
vita_tx_chain
(.clk(wb_clk), .reset(wb_rst),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+ .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
.vita_time(vita_time),
.tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy),
.err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy),
diff --git a/usrp2/top/E1x0/u1e_core.v b/usrp2/top/E1x0/u1e_core.v
index d3495707d..5f2edca1a 100644
--- a/usrp2/top/E1x0/u1e_core.v
+++ b/usrp2/top/E1x0/u1e_core.v
@@ -169,9 +169,10 @@ module u1e_core
.sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0),
.debug() );
- vita_rx_chain #(.BASE(SR_RX_CTRL0), .UNIT(0), .FIFOSIZE(10), .PROT_ENG_FLAGS(0)) vita_rx_chain0
+ vita_rx_chain #(.BASE(SR_RX_CTRL0), .UNIT(0), .FIFOSIZE(10), .PROT_ENG_FLAGS(0), .DSP_NUMBER(0)) vita_rx_chain0
(.clk(wb_clk),.reset(wb_rst),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+ .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
.vita_time(vita_time), .overrun(rx_overrun_dsp0),
.sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0),
.rx_data_o(vita_rx_data0), .rx_dst_rdy_i(vita_rx_dst_rdy0), .rx_src_rdy_o(vita_rx_src_rdy0),
@@ -193,9 +194,10 @@ module u1e_core
.sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1),
.debug() );
- vita_rx_chain #(.BASE(SR_RX_CTRL1), .UNIT(1), .FIFOSIZE(10), .PROT_ENG_FLAGS(0)) vita_rx_chain1
+ vita_rx_chain #(.BASE(SR_RX_CTRL1), .UNIT(1), .FIFOSIZE(10), .PROT_ENG_FLAGS(0), .DSP_NUMBER(1)) vita_rx_chain1
(.clk(wb_clk),.reset(wb_rst),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+ .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
.vita_time(vita_time), .overrun(rx_overrun_dsp1),
.sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1),
.rx_data_o(vita_rx_data1), .rx_dst_rdy_i(vita_rx_dst_rdy1), .rx_src_rdy_o(vita_rx_src_rdy1),
@@ -225,6 +227,7 @@ module u1e_core
vita_tx_chain
(.clk(wb_clk), .reset(wb_rst),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+ .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
.vita_time(vita_time),
.tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy),
.err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy),
diff --git a/usrp2/top/N2x0/u2plus_core.v b/usrp2/top/N2x0/u2plus_core.v
index f04d449be..8b804bb0c 100644
--- a/usrp2/top/N2x0/u2plus_core.v
+++ b/usrp2/top/N2x0/u2plus_core.v
@@ -591,9 +591,10 @@ module u2plus_core
.sample(sample_rx0), .run(run_rx0_d1), .strobe(strobe_rx0),
.debug() );
- vita_rx_chain #(.BASE(SR_RX_CTRL0),.UNIT(0),.FIFOSIZE(DSP_RX_FIFOSIZE)) vita_rx_chain0
+ vita_rx_chain #(.BASE(SR_RX_CTRL0),.UNIT(0),.FIFOSIZE(DSP_RX_FIFOSIZE), .DSP_NUMBER(0)) vita_rx_chain0
(.clk(dsp_clk), .reset(dsp_rst),
.set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+ .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
.vita_time(vita_time), .overrun(overrun0),
.sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0),
.rx_data_o(wr1_dat), .rx_src_rdy_o(wr1_ready_i), .rx_dst_rdy_i(wr1_ready_o),
@@ -615,9 +616,10 @@ module u2plus_core
.sample(sample_rx1), .run(run_rx1_d1), .strobe(strobe_rx1),
.debug() );
- vita_rx_chain #(.BASE(SR_RX_CTRL1),.UNIT(2),.FIFOSIZE(DSP_RX_FIFOSIZE)) vita_rx_chain1
+ vita_rx_chain #(.BASE(SR_RX_CTRL1),.UNIT(2),.FIFOSIZE(DSP_RX_FIFOSIZE), .DSP_NUMBER(1)) vita_rx_chain1
(.clk(dsp_clk), .reset(dsp_rst),
.set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+ .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
.vita_time(vita_time), .overrun(overrun1),
.sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1),
.rx_data_o(wr3_dat), .rx_src_rdy_o(wr3_ready_i), .rx_dst_rdy_i(wr3_ready_o),
@@ -661,13 +663,13 @@ module u2plus_core
wire strobe_tx;
vita_tx_chain #(.BASE(SR_TX_CTRL), .FIFOSIZE(DSP_TX_FIFOSIZE),
- .POST_ENGINE_FIFOSIZE(DSP_TX_FIFOSIZE+1),
.REPORT_ERROR(1), .DO_FLOW_CONTROL(1),
.PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1),
.DSP_NUMBER(0))
vita_tx_chain
(.clk(dsp_clk), .reset(dsp_rst),
.set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+ .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
.vita_time(vita_time),
.tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy),
.err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy),
diff --git a/usrp2/top/USRP2/u2_core.v b/usrp2/top/USRP2/u2_core.v
index d29f31b8f..4b2276e4a 100644
--- a/usrp2/top/USRP2/u2_core.v
+++ b/usrp2/top/USRP2/u2_core.v
@@ -579,9 +579,10 @@ module u2_core
.sample(sample_rx0), .run(run_rx0_d1), .strobe(strobe_rx0),
.debug() );
- vita_rx_chain #(.BASE(SR_RX_CTRL0),.UNIT(0),.FIFOSIZE(DSP_RX_FIFOSIZE)) vita_rx_chain0
+ vita_rx_chain #(.BASE(SR_RX_CTRL0),.UNIT(0),.FIFOSIZE(DSP_RX_FIFOSIZE), .DSP_NUMBER(0)) vita_rx_chain0
(.clk(dsp_clk), .reset(dsp_rst),
.set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+ .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
.vita_time(vita_time), .overrun(overrun0),
.sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0),
.rx_data_o(wr1_dat), .rx_src_rdy_o(wr1_ready_i), .rx_dst_rdy_i(wr1_ready_o),
@@ -603,9 +604,10 @@ module u2_core
.sample(sample_rx1), .run(run_rx1_d1), .strobe(strobe_rx1),
.debug() );
- vita_rx_chain #(.BASE(SR_RX_CTRL1),.UNIT(2),.FIFOSIZE(DSP_RX_FIFOSIZE)) vita_rx_chain1
+ vita_rx_chain #(.BASE(SR_RX_CTRL1),.UNIT(2),.FIFOSIZE(DSP_RX_FIFOSIZE), .DSP_NUMBER(1)) vita_rx_chain1
(.clk(dsp_clk), .reset(dsp_rst),
.set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+ .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
.vita_time(vita_time), .overrun(overrun1),
.sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1),
.rx_data_o(wr3_dat), .rx_src_rdy_o(wr3_ready_i), .rx_dst_rdy_i(wr3_ready_o),
@@ -647,13 +649,13 @@ module u2_core
wire strobe_tx;
vita_tx_chain #(.BASE(SR_TX_CTRL), .FIFOSIZE(DSP_TX_FIFOSIZE),
- .POST_ENGINE_FIFOSIZE(DSP_TX_FIFOSIZE+1),
.REPORT_ERROR(1), .DO_FLOW_CONTROL(1),
.PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1),
.DSP_NUMBER(0))
vita_tx_chain
(.clk(dsp_clk), .reset(dsp_rst),
.set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+ .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
.vita_time(vita_time),
.tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy),
.err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy),
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-15 16:49:47 +0000