diff options
Diffstat (limited to 'usrp2/top/u1_core')
| -rw-r--r-- | usrp2/top/u1_core/.gitignore | 44 | ||||
| -rwxr-xr-x | usrp2/top/u1_core/u1_core.v | 455 |
2 files changed, 0 insertions, 499 deletions
diff --git a/usrp2/top/u1_core/.gitignore b/usrp2/top/u1_core/.gitignore deleted file mode 100644 index 9728395c1..000000000 --- a/usrp2/top/u1_core/.gitignore +++ /dev/null @@ -1,44 +0,0 @@ -*~ -/xst -/_ngo -/_xmsgs -/*.stx -/*.tspec -/*.xml -/*.gyd -/*.ngr -/*.tim -/*.err -/*.lso -/*.bld -/*.cmd_log -/*.ise_ISE_Backup -/*.mfd -/*.vm6 -/*.syr -/*.xst -/*.csv -/*.html -/*.jed -/*.pad -/*.ng* -/*.pnx -/*.rpt -/*.prj -/*_html -/*_log -/*.lfp -/*.bit -/*.bin -/*.vcd -/*.unroutes -/*.drc -/*_map.* -/*_guide.* -/*.twr -/*.twx -/a.out -/*.xpi -/*_pad.txt -/*.bgn -/*.par diff --git a/usrp2/top/u1_core/u1_core.v b/usrp2/top/u1_core/u1_core.v deleted file mode 100755 index 24a57936e..000000000 --- a/usrp2/top/u1_core/u1_core.v +++ /dev/null @@ -1,455 +0,0 @@ -// //////////////////////////////////////////////////////////////////////////////// -// Module Name: u2_core -// //////////////////////////////////////////////////////////////////////////////// - -module u1_core - #(parameter RAM_SIZE=16384) - (input sys_clk, input sys_rst, - input wb_clk, input wb_rst, - - output uart_tx_o, input uart_rx_i, output uart_baud_o, - output [2:0] leds, output [31:0] debug, output [1:0] debug_clk, - - input scl_pad_i, output scl_pad_o, output scl_pad_oen_o, - input sda_pad_i, output sda_pad_o, output sda_pad_oen_o, - - input pps, - output reset_codec, - - input gpif_clk, inout [15:0] gpif_d, input [3:0] gpif_ctl, output [3:0] gpif_rdy, - input [2:0] gpif_misc, - - input [11:0] adc, input rxsync, - output [13:0] dac, output txsync, output txblank, - - // Generic SPI - output sclk, - output mosi, - input miso, - output [3:0] sen, - - // GPIO to DBoards - inout [15:0] io_tx, - inout [15:0] io_rx, - - input sim_mode - ); - - wire [7:0] set_addr; - wire [31:0] set_data; - wire set_stb; - - wire ram_loader_done, ram_loader_rst; - - wire [31:0] status, status_b0, status_b1, status_b2, status_b3, status_b4, status_b5, status_b6, status_b7; - wire bus_error, spi_int, i2c_int, pps_int, timer_int, buffer_int, proc_int, overrun, underrun, uart_tx_int, uart_rx_int; - - wire [31:0] debug_gpio_0, debug_gpio_1; - wire [31:0] atr_lines; - - wire [31:0] debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc, - debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp; - - wire [15:0] ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2; - wire ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2; - wire ser_rx_empty, ser_tx_empty, dsp_rx_empty, dsp_tx_empty, eth_rx_empty, eth_tx_empty, eth_rx_empty2; - - wire serdes_link_up; - wire epoch; - wire [31:0] irq; - - // /////////////////////////////////////////////////////////////////////////////////////////////// - // Wishbone Single Master INTERCON - localparam dw = 32; // Data bus width - localparam aw = 16; // Address bus width, for byte addressibility, 16 = 64K byte memory space - localparam sw = 4; // Select width -- 32-bit data bus with 8-bit granularity. - - wire [dw-1:0] m0_dat_o, m0_dat_i; - wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i, - s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i, - s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, sa_dat_o, sa_dat_i, sb_dat_i, sb_dat_o, - sc_dat_i, sc_dat_o, sd_dat_i, sd_dat_o, se_dat_i, se_dat_o; - wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr; - wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel; - wire m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack; - wire m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb; - wire m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc; - wire m0_err, m0_rty; - wire m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,sa_we,sb_we,sc_we,sd_we, se_we; - - wb_1master #(.decode_w(6), - .s0_addr(6'b0000_00),.s0_mask(6'b100000), - .s1_addr(6'b1000_00),.s1_mask(6'b110000), - .s2_addr(6'b1100_00),.s2_mask(6'b111111), - .s3_addr(6'b1100_01),.s3_mask(6'b111111), - .s4_addr(6'b1100_10),.s4_mask(6'b111111), - .s5_addr(6'b1100_11),.s5_mask(6'b111111), - .s6_addr(6'b1101_00),.s6_mask(6'b111111), - .s7_addr(6'b1101_01),.s7_mask(6'b111111), - .s8_addr(6'b1101_10),.s8_mask(6'b111111), - .s9_addr(6'b1101_11),.s9_mask(6'b111111), - .sa_addr(6'b1110_00),.sa_mask(6'b111111), - .sb_addr(6'b1110_01),.sb_mask(6'b111111), - .sc_addr(6'b1110_10),.sc_mask(6'b111111), - .sd_addr(6'b1110_11),.sd_mask(6'b111111), - .se_addr(6'b1111_00),.se_mask(6'b111111), - .sf_addr(6'b1111_01),.sf_mask(6'b111111), - .dw(dw),.aw(aw),.sw(sw)) wb_1master - (.clk_i(wb_clk),.rst_i(wb_rst), - .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i), - .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), - .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o (s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), - .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0), - .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o (s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), - .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0), - .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o (s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), - .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0), - .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o (s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), - .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0), - .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o (s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), - .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0), - .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o (s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), - .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0), - .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o (s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), - .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0), - .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o (s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), - .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0), - .s8_dat_o(s8_dat_o),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o (s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb), - .s8_dat_i(s8_dat_i),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0), - .s9_dat_o(s9_dat_o),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o (s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb), - .s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0), - .sa_dat_o(sa_dat_o),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb), - .sa_dat_i(sa_dat_i),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0), - .sb_dat_o(sb_dat_o),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb), - .sb_dat_i(sb_dat_i),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0), - .sc_dat_o(sc_dat_o),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb), - .sc_dat_i(sc_dat_i),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0), - .sd_dat_o(sd_dat_o),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb), - .sd_dat_i(sd_dat_i),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0), - .se_dat_o(se_dat_o),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb), - .se_dat_i(se_dat_i),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0), - .sf_dat_i(0),.sf_ack_i(0),.sf_err_i(0),.sf_rty_i(0) ); - - // /////////////////////////////////////////////////////////////////// - // RAM Loader - - wire [31:0] ram_loader_dat, iwb_dat; - wire [15:0] ram_loader_adr, iwb_adr; - wire [3:0] ram_loader_sel; - wire ram_loader_stb, ram_loader_we, ram_loader_ack; - wire iwb_ack, iwb_stb; - ram_loader #(.AWIDTH(16),.RAM_SIZE(RAM_SIZE)) - ram_loader (.clk_i(wb_clk),.rst_i(ram_loader_rst), - // CPLD Interface - .cfg_clk_i(cpld_clk), - .cfg_data_i(cpld_din), - .start_o(cpld_start_int), - .mode_o(cpld_mode_int), - .done_o(cpld_done_int), - .detached_i(cpld_detached), - // Wishbone Interface - .wb_dat_o(ram_loader_dat),.wb_adr_o(ram_loader_adr), - .wb_stb_o(ram_loader_stb),.wb_cyc_o(),.wb_sel_o(ram_loader_sel), - .wb_we_o(ram_loader_we),.wb_ack_i(ram_loader_ack), - .ram_loader_done_o(ram_loader_done)); - - // ///////////////////////////////////////////////////////////////////////// - // Processor - aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1)) - aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst), - // Instruction Wishbone bus to I-RAM - .iwb_stb_o(iwb_stb),.iwb_adr_o(iwb_adr), - .iwb_dat_i(iwb_dat),.iwb_ack_i(iwb_ack), - // Data Wishbone bus to system bus fabric - .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr), - .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc), - // Interrupts and exceptions - .sys_int_i(proc_int),.sys_exc_i(bus_error) ); - - assign bus_error = m0_err | m0_rty; - - // ///////////////////////////////////////////////////////////////////////// - // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone - // I-port connects directly to processor and ram loader - - wire flush_icache; - ram_harv_cache #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6)) - sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - - .ram_loader_adr_i(ram_loader_adr[14:0]), .ram_loader_dat_i(ram_loader_dat), - .ram_loader_stb_i(ram_loader_stb), .ram_loader_sel_i(ram_loader_sel), - .ram_loader_we_i(ram_loader_we), .ram_loader_ack_o(ram_loader_ack), - .ram_loader_done_i(ram_loader_done), - - .iwb_adr_i(iwb_adr[14:0]), .iwb_stb_i(iwb_stb), - .iwb_dat_o(iwb_dat), .iwb_ack_o(iwb_ack), - - .dwb_adr_i(s0_adr[14:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), - .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel), - .flush_icache(flush_icache)); - - setting_reg #(.my_addr(7)) sr_icache (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(),.changed(flush_icache)); - - // ///////////////////////////////////////////////////////////////////////// - // Buffer Pool, slave #1 - wire rd0_ready_i, rd0_ready_o; - wire rd1_ready_i, rd1_ready_o; - wire rd2_ready_i, rd2_ready_o; - wire rd3_ready_i, rd3_ready_o; - wire [3:0] rd0_flags, rd1_flags, rd2_flags, rd3_flags; - wire [31:0] rd0_dat, rd1_dat, rd2_dat, rd3_dat; - - wire wr0_ready_i, wr0_ready_o; - wire wr1_ready_i, wr1_ready_o; - wire wr2_ready_i, wr2_ready_o; - wire wr3_ready_i, wr3_ready_o; - wire [3:0] wr0_flags, wr1_flags, wr2_flags, wr3_flags; - wire [31:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; - - buffer_pool #(.BUF_SIZE(9), .SET_ADDR(64)) buffer_pool - (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), - .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(), - - .stream_clk(dsp_clk), .stream_rst(dsp_rst), - .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .status(status),.sys_int_o(buffer_int), - - .s0(status_b0),.s1(status_b1),.s2(status_b2),.s3(status_b3), - .s4(status_b4),.s5(status_b5),.s6(status_b6),.s7(status_b7), - - // Write Interfaces - .wr0_data_i(wr0_dat), .wr0_flags_i(wr0_flags), .wr0_ready_i(wr0_ready_i), .wr0_ready_o(wr0_ready_o), - .wr1_data_i(wr1_dat), .wr1_flags_i(wr1_flags), .wr1_ready_i(wr1_ready_i), .wr1_ready_o(wr1_ready_o), - .wr2_data_i(wr2_dat), .wr2_flags_i(wr2_flags), .wr2_ready_i(wr2_ready_i), .wr2_ready_o(wr2_ready_o), - .wr3_data_i(wr3_dat), .wr3_flags_i(wr3_flags), .wr3_ready_i(wr3_ready_i), .wr3_ready_o(wr3_ready_o), - // Read Interfaces - .rd0_data_o(rd0_dat), .rd0_flags_o(rd0_flags), .rd0_ready_i(rd0_ready_i), .rd0_ready_o(rd0_ready_o), - .rd1_data_o(rd1_dat), .rd1_flags_o(rd1_flags), .rd1_ready_i(rd1_ready_i), .rd1_ready_o(rd1_ready_o), - .rd2_data_o(rd2_dat), .rd2_flags_o(rd2_flags), .rd2_ready_i(rd2_ready_i), .rd2_ready_o(rd2_ready_o), - .rd3_data_o(rd3_dat), .rd3_flags_o(rd3_flags), .rd3_ready_i(rd3_ready_i), .rd3_ready_o(rd3_ready_o) - ); - - wire [31:0] status_enc; - priority_enc priority_enc (.in({16'b0,status[15:0]}), .out(status_enc)); - - // ///////////////////////////////////////////////////////////////////////// - // SPI -- Slave #2 - spi_top shared_spi - (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o), - .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), - .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(spi_int), - .ss_pad_o(sen), - .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) ); - - // ///////////////////////////////////////////////////////////////////////// - // I2C -- Slave #3 - i2c_master_top #(.ARST_LVL(1)) - i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), - .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_o[7:0]),.wb_dat_o(s3_dat_i[7:0]), - .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), - .wb_ack_o(s3_ack),.wb_inta_o(i2c_int), - .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), - .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); - - assign s3_dat_i[31:8] = 24'd0; - - // ///////////////////////////////////////////////////////////////////////// - // GPIOs -- Slave #4 - nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst), - .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), - .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack), - .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), - .gpio( {io_tx,io_rx} ) ); - - // ///////////////////////////////////////////////////////////////////////// - // Buffer Pool Status -- Slave #5 - - reg [31:0] cycle_count; - always @(posedge wb_clk) - if(wb_rst) - cycle_count <= 0; - else - cycle_count <= cycle_count + 1; - - wb_readback_mux buff_pool_status - (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), - .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack), - - .word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3), - .word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7), - .word08(status),.word09({sim_mode,31'b0}),.word10(32'b0), - .word11(32'b0),.word12(32'b0),.word13(irq),.word14(status_enc),.word15(cycle_count) - ); - - // ///////////////////////////////////////////////////////////////////////// - // Settings Bus -- Slave #7 - settings_bus settings_bus - (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o), - .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack), - .sys_clk(dsp_clk),.strobe(set_stb),.addr(set_addr),.data(set_data)); - - assign s7_dat_i = 32'd0; - - // Output control lines - setting_reg #(.my_addr(0)) sr_clk (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr), - .in(set_data),.out(clock_outs),.changed()); - - // ///////////////////////////////////////////////////////////////////////// - // LEDS - // register 8 determines whether leds are controlled by SW or not - // 1 = controlled by HW, 0 = by SW - // In Rev3 there are only 6 leds, and the highest one is on the ETH connector - - wire [7:0] led_hw = 0; - - setting_reg #(.my_addr(3)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(led_sw),.changed()); - setting_reg #(.my_addr(8)) sr_led_src (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(led_src),.changed()); - - assign leds = (led_src & led_hw) | (~led_src & led_sw); - - // ///////////////////////////////////////////////////////////////////////// - // Interrupt Controller, Slave #8 - - assign irq= {{8'b0}, - {8'b0}, - {6'b0, uart_tx_int, uart_rx_int}, - {pps_int,overrun,underrun,1'b0,i2c_int,spi_int,timer_int,buffer_int}}; - - pic pic(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[3:2]), - .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int), - .irq(irq) ); - - // ///////////////////////////////////////////////////////////////////////// - // Master Timer, Slave #9 - - wire [31:0] master_time; - timer timer - (.wb_clk_i(wb_clk),.rst_i(wb_rst), - .cyc_i(s9_cyc),.stb_i(s9_stb),.adr_i(s9_adr[4:2]), - .we_i(s9_we),.dat_i(s9_dat_o),.dat_o(s9_dat_i),.ack_o(s9_ack), - .sys_clk_i(dsp_clk),.master_time_i(master_time),.int_o(timer_int) ); - - // ///////////////////////////////////////////////////////////////////////// - // UART, Slave #10 - - simple_uart #(.TXDEPTH(3),.RXDEPTH(3)) uart // depth of 3 is 128 entries - (.clk_i(wb_clk),.rst_i(wb_rst), - .we_i(sa_we),.stb_i(sa_stb),.cyc_i(sa_cyc),.ack_o(sa_ack), - .adr_i(sa_adr[4:2]),.dat_i(sa_dat_o),.dat_o(sa_dat_i), - .rx_int_o(uart_rx_int),.tx_int_o(uart_tx_int), - .tx_o(uart_tx_o),.rx_i(uart_rx_i),.baud_o(uart_baud_o)); - - // ///////////////////////////////////////////////////////////////////////// - // ATR Controller, Slave #11 - - wire run_rx, run_tx; - reg run_rx_d1; - always @(posedge dsp_clk) - run_rx_d1 <= run_rx; - - atr_controller atr_controller - (.clk_i(wb_clk),.rst_i(wb_rst), - .adr_i(sb_adr[5:0]),.sel_i(sb_sel),.dat_i(sb_dat_o),.dat_o(sb_dat_i), - .we_i(sb_we),.stb_i(sb_stb),.cyc_i(sb_cyc),.ack_o(sb_ack), - .run_rx(run_rx_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) ); - - // ////////////////////////////////////////////////////////////////////////// - // Time Sync, Slave #12 - - reg pps_posedge, pps_negedge, pps_pos_d1, pps_neg_d1; - always @(negedge dsp_clk) pps_negedge <= pps; - always @(posedge dsp_clk) pps_posedge <= pps; - always @(posedge dsp_clk) pps_pos_d1 <= pps_posedge; - always @(posedge dsp_clk) pps_neg_d1 <= pps_negedge; - - wire pps_o; - time_sync time_sync - (.wb_clk_i(wb_clk),.rst_i(wb_rst), - .cyc_i(sc_cyc),.stb_i(sc_stb),.adr_i(sc_adr[4:2]), - .we_i(sc_we),.dat_i(sc_dat_o),.dat_o(sc_dat_i),.ack_o(sc_ack), - .sys_clk_i(dsp_clk),.master_time_o(master_time), - .pps_posedge(pps_posedge),.pps_negedge(pps_negedge), - .exp_pps_in(),.exp_pps_out(), - .int_o(pps_int),.epoch_o(epoch),.pps_o(pps_o) ); - - // ///////////////////////////////////////////////////////////////////////// - // DSP - wire [31:0] sample_rx, sample_tx; - wire strobe_rx, strobe_tx; - - rx_control #(.FIFOSIZE(10)) rx_control - (.clk(dsp_clk), .rst(dsp_rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .master_time(master_time),.overrun(overrun), - .wr_dat_o(wr1_dat), .wr_flags_o(wr1_flags), .wr_ready_o(wr1_ready_i), .wr_ready_i(wr1_ready_o), - .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), - .fifo_occupied(dsp_rx_occ),.fifo_full(dsp_rx_full),.fifo_empty(dsp_rx_empty), - .debug_rx(debug_rx) ); - - dsp_core_rx dsp_core_rx - (.clk(dsp_clk),.rst(dsp_rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), - .sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx), - .debug(debug_rx_dsp) ); - - tx_control #(.FIFOSIZE(10)) tx_control - (.clk(dsp_clk), .rst(dsp_rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .master_time(master_time),.underrun(underrun), - .rd_dat_i(rd1_dat), .rd_flags_i(rd1_flags), .rd_ready_i(rd1_ready_o), .rd_ready_o(rd1_ready_i), - .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), - .fifo_occupied(dsp_tx_occ),.fifo_full(dsp_tx_full),.fifo_empty(dsp_tx_empty), - .debug(debug_txc) ); - - dsp_core_tx dsp_core_tx - (.clk(dsp_clk),.rst(dsp_rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .dac_a(dac_a),.dac_b(dac_b), - .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), .debug(debug_tx_dsp) ); - - assign dsp_rst = wb_rst; - - // ///////////////////////////////////////////////////////////////////////////////////////// - // CODEC Interface - - assign txblank = 0; - - always @(posedge dsp_clk) - if(tx_strobe) - begin - dac <= dac_a; - txsync <= 0; - end - else - begin - dac <= dac_b; - txsync <= 1; - end - - always @(posedge dsp_clk) - if(rxsync) - begin - adc_a_hold <= adc; - rx_strobe <= 0; - end - else - begin - adc_a <= adc_a_hold; - adc_b <= adc; - rx_strobe <= 1; - end - - // ///////////////////////////////////////////////////////////////////////////////////////// - // Debug Pins - - assign debug_clk[0] = 0; - assign debug_clk[1] = 0; - assign debug = 0; - - -endmodule // u1_core |