diff options
Diffstat (limited to 'usrp2/top/safe_u1plus')
| -rw-r--r-- | usrp2/top/safe_u1plus/.gitignore | 1 | ||||
| -rw-r--r-- | usrp2/top/safe_u1plus/Makefile | 122 | ||||
| -rw-r--r-- | usrp2/top/safe_u1plus/safe_u1plus.ucf | 171 | ||||
| -rw-r--r-- | usrp2/top/safe_u1plus/safe_u1plus.v | 28 |
4 files changed, 0 insertions, 322 deletions
diff --git a/usrp2/top/safe_u1plus/.gitignore b/usrp2/top/safe_u1plus/.gitignore deleted file mode 100644 index 1b2211df0..000000000 --- a/usrp2/top/safe_u1plus/.gitignore +++ /dev/null @@ -1 +0,0 @@ -build* diff --git a/usrp2/top/safe_u1plus/Makefile b/usrp2/top/safe_u1plus/Makefile deleted file mode 100644 index 33a2a51c7..000000000 --- a/usrp2/top/safe_u1plus/Makefile +++ /dev/null @@ -1,122 +0,0 @@ -# -# Copyright 2008 Ettus Research LLC -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -################################################## -# xtclsh Shell and tcl Script Path -################################################## -#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh -XTCLSH := xtclsh -ISE_HELPER := ../tcl/ise_helper.tcl - -################################################## -# Project Setup -################################################## -BUILD_DIR := build/ -export TOP_MODULE := safe_u1plus -export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise - -################################################## -# Project Properties -################################################## -export PROJECT_PROPERTIES := \ -family "Spartan3A" \ -device XC3S1400A \ -package ft256 \ -speed -4 \ -top_level_module_type "HDL" \ -synthesis_tool "XST (VHDL/Verilog)" \ -simulator "ISE Simulator (VHDL/Verilog)" \ -"Preferred Language" "Verilog" \ -"Enable Message Filtering" FALSE \ -"Display Incremental Messages" FALSE - -################################################## -# Sources -################################################## -export SOURCE_ROOT := ../../../ -export SOURCES := \ -top/safe_u1plus/safe_u1plus.ucf \ -top/safe_u1plus/safe_u1plus.v - -################################################## -# Process Properties -################################################## -export SYNTHESIZE_PROPERTIES := \ -"Pack I/O Registers into IOBs" Yes \ -"Optimization Effort" High \ -"Optimize Instantiated Primitives" TRUE \ -"Register Balancing" Yes \ -"Use Clock Enable" Auto \ -"Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto - -export TRANSLATE_PROPERTIES := \ -"Macro Search Path" "$(shell pwd)/../../coregen/" - -export MAP_PROPERTIES := \ -"Allow Logic Optimization Across Hierarchy" TRUE \ -"Map to Input Functions" 4 \ -"Optimization Strategy (Cover Mode)" Speed \ -"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ -"Perform Timing-Driven Packing and Placement" TRUE \ -"Map Effort Level" High \ -"Extra Effort" Normal \ -"Combinatorial Logic Optimization" TRUE \ -"Register Duplication" TRUE - -export PLACE_ROUTE_PROPERTIES := \ -"Place & Route Effort Level (Overall)" High - -export STATIC_TIMING_PROPERTIES := \ -"Number of Paths in Error/Verbose Report" 10 \ -"Report Type" "Error Report" - -export GEN_PROG_FILE_PROPERTIES := \ -"Configuration Rate" 6 \ -"Create Binary Configuration File" TRUE \ -"Done (Output Events)" 5 \ -"Enable Bitstream Compression" TRUE \ -"Enable Outputs (Output Events)" 6 - -export SIM_MODEL_PROPERTIES := "" - -################################################## -# Make Options -################################################## -all: - @echo make proj, check, synth, bin, or clean - -proj: - PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER) - -check: - PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER) - -synth: - PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER) - -bin: - PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER) - -clean: - rm -rf $(BUILD_DIR) - - diff --git a/usrp2/top/safe_u1plus/safe_u1plus.ucf b/usrp2/top/safe_u1plus/safe_u1plus.ucf deleted file mode 100644 index a0c743525..000000000 --- a/usrp2/top/safe_u1plus/safe_u1plus.ucf +++ /dev/null @@ -1,171 +0,0 @@ -NET "debug_led<2>" LOC = "R2" ; -NET "debug_led<1>" LOC = "N4" ; -NET "debug_led<0>" LOC = "P4" ; -NET "reset_n" LOC = "D5" ; -NET "CLK_FPGA_P" LOC = "R7" ; -NET "CLK_FPGA_N" LOC = "T7" ; - -#NET "fpga_cfg_prog_b" LOC = "A2" ; -#NET "fpga_cfg_done" LOC = "T15" ; -#NET "fpga_cfg_din" LOC = "T14" ; -#NET "fpga_cfg_cclk" LOC = "R14" ; -NET "fpga_cfg_init_b" LOC = "T12" ; - - -#NET "TMS" LOC = "B2" ; -#NET "TDO" LOC = "B16" ; -#NET "TDI" LOC = "B1" ; -#NET "TCK" LOC = "A15" ; -#NET "GPIF_D07" LOC = "N12" ; -#NET "GPIF_D06" LOC = "P13" ; -#NET "GPIF_D05" LOC = "P11" ; -#NET "GPIF_RDY3" LOC = "N11" ; -#NET "GPIF_RDY2" LOC = "T10" ; -#NET "GPIF_RDY1" LOC = "T4" ; -#NET "GPIF_RDY0" LOC = "R5" ; -#NET "cgen_st_status" LOC = "P6" ; -#NET "GPIF_CTL3" LOC = "N5" ; -#NET "GPIF_CTL2" LOC = "M11" ; -#NET "GPIF_CTL1" LOC = "M9" ; -#NET "GPIF_CTL0" LOC = "M7" ; -#NET "SDA_FPGA" LOC = "T13" ; -#NET "SCL_FPGA" LOC = "R13" ; -#NET "FX2_PA7_FLAGD" LOC = "P12" ; -#NET "mystery_bus_2" LOC = "T11" ; -#NET "FX2_PA6_PKTEND" LOC = "R11" ; -#NET "FX2_PA2_SLOE" LOC = "P10" ; -#NET "GPIF_D15" LOC = "P7" ; -#NET "GPIF_D14" LOC = "N8" ; -#NET "GPIF_D13" LOC = "T5" ; -#NET "GPIF_D12" LOC = "T6" ; -#NET "GPIF_D11" LOC = "N6" ; -#NET "GPIF_D10" LOC = "P5" ; -#NET "GPIF_D09" LOC = "R3" ; -#NET "GPIF_D08" LOC = "T3" ; -#NET "cgen_ref_sel" LOC = "T2" ; -#NET "GPIF_D04" LOC = "R9" ; -#NET "GPIF_D03" LOC = "T9" ; -#NET "GPIF_D02" LOC = "N9" ; -#NET "GPIF_D01" LOC = "P9" ; -#NET "GPIF_D00" LOC = "P8" ; -#NET "IFCLK" LOC = "T8" ; -#NET "cgen_sync_b" LOC = "H15" ; -#NET "FPGA_TXD" LOC = "H16" ; -#NET "debug_00" LOC = "K16" ; -#NET "debug_01" LOC = "J16" ; -#NET "debug_clk0" LOC = "K15" ; -#NET "debug_clk1" LOC = "K14" ; -#NET "debug_02" LOC = "C16" ; -#NET "debug_03" LOC = "C15" ; -#NET "debug_04" LOC = "E13" ; -#NET "debug_05" LOC = "D14" ; -#NET "debug_06" LOC = "D16" ; -#NET "debug_07" LOC = "D15" ; -#NET "debug_08" LOC = "E14" ; -#NET "debug_09" LOC = "F13" ; -#NET "debug_10" LOC = "G13" ; -#NET "debug_11" LOC = "F14" ; -#NET "debug_12" LOC = "E16" ; -#NET "debug_13" LOC = "F15" ; -#NET "debug_14" LOC = "H13" ; -#NET "debug_15" LOC = "G14" ; -#NET "debug_16" LOC = "G16" ; -#NET "debug_17" LOC = "F16" ; -#NET "debug_18" LOC = "J12" ; -#NET "debug_19" LOC = "J13" ; -#NET "debug_20" LOC = "L14" ; -#NET "debug_21" LOC = "L16" ; -#NET "debug_22" LOC = "M15" ; -#NET "debug_23" LOC = "M16" ; -#NET "debug_24" LOC = "L13" ; -#NET "debug_25" LOC = "K13" ; -#NET "debug_26" LOC = "P16" ; -#NET "debug_27" LOC = "N16" ; -#NET "debug_28" LOC = "R15" ; -#NET "debug_29" LOC = "P15" ; -#NET "debug_30" LOC = "N13" ; -#NET "debug_31" LOC = "N14" ; -#NET "PPS_IN" LOC = "M14" ; -#NET "cgen_st_ld" LOC = "M13" ; -#NET "cgen_st_refmon" LOC = "J14" ; -#NET "FPGA_RXD" LOC = "H12" ; -#NET "DA10" LOC = "A8" ; -#NET "DA09" LOC = "B8" ; -#NET "DA08" LOC = "C8" ; -#NET "DA07" LOC = "D8" ; -#NET "DA06" LOC = "C9" ; -#NET "DA05" LOC = "A9" ; -#NET "DA04" LOC = "C10" ; -#NET "DA03" LOC = "D9" ; -#NET "SCLK_CODEC" LOC = "K3" ; -#NET "TXBLANK" LOC = "K1" ; -#NET "TXSYNC" LOC = "J2" ; -#NET "TX00" LOC = "J1" ; -#NET "TX01" LOC = "H3" ; -#NET "TX02" LOC = "J3" ; -#NET "TX03" LOC = "G2" ; -#NET "TX04" LOC = "H1" ; -#NET "TX05" LOC = "N3" ; -#NET "TX06" LOC = "M4" ; -#NET "TX07" LOC = "R1" ; -#NET "TX08" LOC = "P2" ; -#NET "TX09" LOC = "P1" ; -#NET "TX10" LOC = "M1" ; -#NET "TX11" LOC = "N1" ; -#NET "TX12" LOC = "M3" ; -#NET "TX13" LOC = "L4" ; -#NET "io_tx_00" LOC = "K4" ; -#NET "io_tx_01" LOC = "L3" ; -#NET "io_tx_02" LOC = "L2" ; -#NET "io_tx_03" LOC = "F1" ; -#NET "io_tx_04" LOC = "F3" ; -#NET "io_tx_05" LOC = "G3" ; -#NET "io_tx_06" LOC = "E3" ; -#NET "io_tx_07" LOC = "E2" ; -#NET "io_tx_08" LOC = "E4" ; -#NET "io_tx_09" LOC = "F4" ; -#NET "io_tx_10" LOC = "D1" ; -#NET "io_tx_11" LOC = "E1" ; -#NET "io_tx_12" LOC = "D4" ; -#NET "io_tx_13" LOC = "D3" ; -#NET "io_tx_14" LOC = "C2" ; -#NET "io_tx_15" LOC = "C1" ; -#NET "MISO_AUX" LOC = "J5" ; -#NET "MISO_CODEC" LOC = "G4" ; -#NET "MISO_TX_DB" LOC = "J4" ; -#NET "SEN_TX_DB" LOC = "N2" ; -#NET "MOSI_TX_DB" LOC = "L1" ; -#NET "SCLK_TX_DB" LOC = "G1" ; -#NET "DA02" LOC = "A3" ; -#NET "DA01" LOC = "B3" ; -#NET "DA00" LOC = "A4" ; -#NET "SEN_RX_DB" LOC = "B4" ; -#NET "MOSI_RX_DB" LOC = "A5" ; -#NET "SCLK_RX_DB" LOC = "C5" ; -#NET "io_rx_00" LOC = "D7" ; -#NET "io_rx_01" LOC = "C6" ; -#NET "io_rx_02" LOC = "A6" ; -#NET "io_rx_03" LOC = "B6" ; -#NET "io_rx_04" LOC = "E9" ; -#NET "io_rx_05" LOC = "A7" ; -#NET "io_rx_06" LOC = "C7" ; -#NET "io_rx_07" LOC = "B10" ; -#NET "io_rx_08" LOC = "A10" ; -#NET "io_rx_09" LOC = "C11" ; -#NET "io_rx_10" LOC = "A11" ; -#NET "io_rx_11" LOC = "D11" ; -#NET "io_rx_12" LOC = "B12" ; -#NET "io_rx_13" LOC = "A12" ; -#NET "io_rx_14" LOC = "A14" ; -#NET "io_rx_15" LOC = "A13" ; -#NET "SEN_AUX" LOC = "C12" ; -#NET "SCLK_AUX" LOC = "D12" ; -#NET "reset_codec" LOC = "B14" ; -#NET "SEN_CODEC" LOC = "D13" ; -#NET "MOSI_CODEC" LOC = "C13" ; -#NET "MISO_RX_DB" LOC = "E6" ; -#NET "mystery_bus_1" LOC = "C4" ; -#NET "mystery_bus_0" LOC = "E7" ; -#NET "RXSYNC" LOC = "D10" ; -#NET "DA11" LOC = "B15" ; - diff --git a/usrp2/top/safe_u1plus/safe_u1plus.v b/usrp2/top/safe_u1plus/safe_u1plus.v deleted file mode 100644 index e55c7f0be..000000000 --- a/usrp2/top/safe_u1plus/safe_u1plus.v +++ /dev/null @@ -1,28 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// - -module safe_u1plus - (input CLK_FPGA_P, input CLK_FPGA_N, - input reset_n, - output [2:0] debug_led, // LED4 is shared w/INIT_B - output fpga_cfg_init_b - ); - - assign fpga_cfg_init_b = 1; - - // FPGA-specific pins connections - wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready; - - IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); - defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; - - reg [31:0] ctr; - - always @(posedge clk_fpga) - ctr <= ctr + 1; - - assign debug_led[1:0] = ~ctr[26:25]; - - assign debug_led[2] = ~reset_n; - -endmodule // safe_u1plus |