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-rw-r--r--usrp2/top/USRP2/u2_core.v4
1 files changed, 2 insertions, 2 deletions
diff --git a/usrp2/top/USRP2/u2_core.v b/usrp2/top/USRP2/u2_core.v
index d8fe8cf10..aed69a9bd 100644
--- a/usrp2/top/USRP2/u2_core.v
+++ b/usrp2/top/USRP2/u2_core.v
@@ -1,5 +1,5 @@
//
-// Copyright 2011-2012 Ettus Research LLC
+// Copyright 2011-2013 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
@@ -456,7 +456,7 @@ module u2_core
// Buffer Pool Status -- Slave #5
//compatibility number -> increment when the fpga has been sufficiently altered
- localparam compat_num = {16'd10, 16'd0}; //major, minor
+ localparam compat_num = {16'd10, 16'd1}; //major, minor
wire [31:0] irq_readback = {19'b0, spi_ready, clk_status, serdes_link_up, 10'b0};