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-rw-r--r--usrp2/sdr_lib/ddc_chain.v34
-rw-r--r--usrp2/sdr_lib/dspengine_16to8.v38
-rw-r--r--usrp2/sdr_lib/duc_chain.v10
3 files changed, 45 insertions, 37 deletions
diff --git a/usrp2/sdr_lib/ddc_chain.v b/usrp2/sdr_lib/ddc_chain.v
index 86ff2001b..7de0e6ae6 100644
--- a/usrp2/sdr_lib/ddc_chain.v
+++ b/usrp2/sdr_lib/ddc_chain.v
@@ -37,6 +37,7 @@ module ddc_chain
wire [31:0] phase_inc;
reg [31:0] phase;
+ wire [17:0] scale_factor;
wire [24:0] i_cordic, q_cordic;
wire [23:0] i_cordic_clip, q_cordic_clip;
wire [23:0] i_cic, q_cic;
@@ -54,13 +55,11 @@ module ddc_chain
setting_reg #(.my_addr(BASE+0)) sr_0
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(phase_inc),.changed());
-
- /*
- setting_reg #(.my_addr(BASE+1)) sr_1
+
+ setting_reg #(.my_addr(BASE+1), .width(18)) sr_1
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
- .in(set_data),.out({scale_i,scale_q}),.changed());
- */
-
+ .in(set_data),.out(scale_factor),.changed());
+
setting_reg #(.my_addr(BASE+2), .width(10)) sr_2
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out({enable_hb1, enable_hb2, cic_decim_rate}),.changed());
@@ -138,14 +137,33 @@ module ddc_chain
(.clk(clk),.rst(rst),.bypass(~enable_hb2),.run(run),.cpi(cpi_hb),
.stb_in(strobe_hb1),.data_in(q_hb1),.stb_out(),.data_out(q_hb2));
+ //scalar operation (gain of 6 bits)
+ wire [35:0] prod_i, prod_q;
+
+ MULT18X18S mult_i
+ (.P(prod_i), .A(i_hb2[23:6]), .B(scale_factor), .C(clk), .CE(strobe_hb2), .R(rst) );
+ MULT18X18S mult_q
+ (.P(prod_q), .A(q_hb2[23:6]), .B(scale_factor), .C(clk), .CE(strobe_hb2), .R(rst) );
+
+ //pipeline for the multiplier (gain of 10 bits)
+ reg [23:0] prod_reg_i, prod_reg_q;
+ reg strobe_mult;
+
+ always @(posedge clk) begin
+ strobe_mult <= strobe_hb2;
+ prod_reg_i <= prod_i[33:10];
+ prod_reg_q <= prod_q[33:10];
+ end
+
// Round final answer to 16 bits
wire [31:0] ddc_chain_out;
wire ddc_chain_stb;
+
round_sd #(.WIDTH_IN(24),.WIDTH_OUT(16)) round_i
- (.clk(clk),.reset(rst), .in(i_hb2),.strobe_in(strobe_hb2), .out(ddc_chain_out[31:16]), .strobe_out(ddc_chain_stb));
+ (.clk(clk),.reset(rst), .in(prod_reg_i),.strobe_in(strobe_mult), .out(ddc_chain_out[31:16]), .strobe_out(ddc_chain_stb));
round_sd #(.WIDTH_IN(24),.WIDTH_OUT(16)) round_q
- (.clk(clk),.reset(rst), .in(q_hb2),.strobe_in(strobe_hb2), .out(ddc_chain_out[15:0]), .strobe_out());
+ (.clk(clk),.reset(rst), .in(prod_reg_q),.strobe_in(strobe_mult), .out(ddc_chain_out[15:0]), .strobe_out());
custom_dsp_rx #(.DSPNO(DSPNO)) custom(
.clock(clk), .reset(rst), .enable(run),
diff --git a/usrp2/sdr_lib/dspengine_16to8.v b/usrp2/sdr_lib/dspengine_16to8.v
index 53c5d29da..448c57d35 100644
--- a/usrp2/sdr_lib/dspengine_16to8.v
+++ b/usrp2/sdr_lib/dspengine_16to8.v
@@ -1,5 +1,5 @@
-// Copyright 2011 Ettus Research LLC
+// Copyright 2011-2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
@@ -32,13 +32,11 @@ module dspengine_16to8
input [35:0] access_dat_i
);
- wire convert;
- wire [17:0] scale_factor;
-
- setting_reg #(.my_addr(BASE),.width(19)) sr_16to8
+ wire convert;
+ setting_reg #(.my_addr(BASE),.width(1)) sr_16to8
(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
- .in(set_data),.out({convert,scale_factor}),.changed());
-
+ .in(set_data),.out(convert),.changed());
+
reg [2:0] dsp_state;
localparam DSP_IDLE = 0;
localparam DSP_PARSE_HEADER = 1;
@@ -63,7 +61,7 @@ module dspengine_16to8
wire [15:0] scaled_i, scaled_q;
wire [7:0] i8, q8;
reg [7:0] i8_reg, q8_reg;
- wire stb_read, stb_mult, stb_clip, stb_round, val_read, val_mult, val_clip, val_round;
+ wire stb_read, stb_clip, val_read, val_clip;
wire stb_out, stb_reg;
reg even;
@@ -193,29 +191,21 @@ module dspengine_16to8
wire [15:0] i16 = access_dat_i[31:16];
wire [15:0] q16 = access_dat_i[15:0];
- pipectrl #(.STAGES(4), .TAGWIDTH(2)) pipectrl
+ pipectrl #(.STAGES(2), .TAGWIDTH(2)) pipectrl
(.clk(clk), .reset(reset),
.src_rdy_i(send_to_pipe), .dst_rdy_o(), // dst_rdy_o will always be 1 since dst_rdy_i is 1, below
.src_rdy_o(stb_out), .dst_rdy_i(1), // always accept output of chain
- .strobes({stb_round,stb_clip,stb_mult,stb_read}), .valids({val_round,val_clip,val_mult,val_read}),
+ .strobes({stb_clip,stb_read}), .valids({val_clip,val_read}),
.tag_i({last,even}), .tag_o({last_o,even_o}));
always @(posedge clk)
if(stb_out & ~even_o)
{i8_reg,q8_reg} <= {i8,q8};
-
- MULT18X18S mult_i
- (.P(prod_i), .A(scale_factor), .B({i16,2'b00}), .C(clk), .CE(stb_mult), .R(reset) );
- clip_reg #(.bits_in(24),.bits_out(16),.STROBED(1)) clip_i
- (.clk(clk), .in(prod_i[35:12]), .out(scaled_i), .strobe_in(stb_clip), .strobe_out());
- round_sd #(.WIDTH_IN(16),.WIDTH_OUT(8),.DISABLE_SD(1)) round_i
- (.clk(clk), .reset(reset), .in(scaled_i), .strobe_in(stb_round), .out(i8), .strobe_out());
-
- MULT18X18S mult_q
- (.P(prod_q), .A(scale_factor), .B({q16,2'b00}), .C(clk), .CE(stb_mult), .R(reset) );
- clip_reg #(.bits_in(24),.bits_out(16),.STROBED(1)) clip_q
- (.clk(clk), .in(prod_q[35:12]), .out(scaled_q), .strobe_in(stb_clip), .strobe_out());
- round_sd #(.WIDTH_IN(16),.WIDTH_OUT(8),.DISABLE_SD(1)) round_q
- (.clk(clk), .reset(reset), .in(scaled_q), .strobe_in(stb_round), .out(q8), .strobe_out());
+
+ clip_reg #(.bits_in(16),.bits_out(8),.STROBED(1)) clip_i
+ (.clk(clk), .in(i16), .out(i8), .strobe_in(stb_clip), .strobe_out());
+
+ clip_reg #(.bits_in(16),.bits_out(8),.STROBED(1)) clip_q
+ (.clk(clk), .in(q16), .out(q8), .strobe_in(stb_clip), .strobe_out());
endmodule // dspengine_16to8
diff --git a/usrp2/sdr_lib/duc_chain.v b/usrp2/sdr_lib/duc_chain.v
index 66d15d0ad..23325ef60 100644
--- a/usrp2/sdr_lib/duc_chain.v
+++ b/usrp2/sdr_lib/duc_chain.v
@@ -34,7 +34,7 @@ module duc_chain
output [31:0] debug
);
- wire [15:0] i, q, scale_i, scale_q;
+ wire [17:0] scale_factor;
wire [31:0] phase_inc;
reg [31:0] phase;
wire [7:0] interp_rate;
@@ -46,9 +46,9 @@ module duc_chain
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(phase_inc),.changed());
- setting_reg #(.my_addr(BASE+1)) sr_1
+ setting_reg #(.my_addr(BASE+1), .width(18)) sr_1
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
- .in(set_data),.out({scale_i,scale_q}),.changed());
+ .in(set_data),.out(scale_factor),.changed());
setting_reg #(.my_addr(BASE+2), .width(10)) sr_2
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
@@ -134,7 +134,7 @@ module duc_chain
MULT18X18S MULT18X18S_inst
(.P(prod_i), // 36-bit multiplier output
.A(da_c[cwidth-1:cwidth-18]), // 18-bit multiplier input
- .B({{2{scale_i[15]}},scale_i}), // 18-bit multiplier input
+ .B(scale_factor), // 18-bit multiplier input
.C(clk), // Clock input
.CE(1), // Clock enable input
.R(rst) // Synchronous reset input
@@ -143,7 +143,7 @@ module duc_chain
MULT18X18S MULT18X18S_inst_2
(.P(prod_q), // 36-bit multiplier output
.A(db_c[cwidth-1:cwidth-18]), // 18-bit multiplier input
- .B({{2{scale_q[15]}},scale_q}), // 18-bit multiplier input
+ .B(scale_factor), // 18-bit multiplier input
.C(clk), // Clock input
.CE(1), // Clock enable input
.R(rst) // Synchronous reset input
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-16 04:52:51 +0000