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+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFGDS.v,v 1.8 2007/07/26 23:22:55 fphillip Exp $
+///////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 1995/2004 Xilinx, Inc.
+// All Right Reserved.
+///////////////////////////////////////////////////////////////////////////////
+// ____ ____
+// / /\/ /
+// /___/ \ / Vendor : Xilinx
+// \ \ \/ Version : 10.1
+// \ \ Description : Xilinx Functional Simulation Library Component
+// / / Differential Signaling Input Clock Buffer
+// /___/ /\ Filename : IBUFGDS.v
+// \ \ / \ Timestamp : Thu Mar 25 16:42:24 PST 2004
+// \___\/\___\
+//
+// Revision:
+// 03/23/04 - Initial version.
+// 05/23/07 - Changed timescale to 1 ps / 1 ps.
+// 07/26/07 - Add else to handle x case for o_out (CR 424214).
+// End Revision
+
+
+`timescale 1 ps / 1 ps
+
+
+module IBUFGDS (O, I, IB);
+
+ parameter CAPACITANCE = "DONT_CARE";
+ parameter DIFF_TERM = "FALSE";
+ parameter IBUF_DELAY_VALUE = "0";
+ parameter IOSTANDARD = "DEFAULT";
+
+ output O;
+ input I, IB;
+
+ reg o_out;
+
+ buf b_0 (O, o_out);
+
+ initial begin
+
+ case (CAPACITANCE)
+
+ "LOW", "NORMAL", "DONT_CARE" : ;
+ default : begin
+ $display("Attribute Syntax Error : The attribute CAPACITANCE on IBUFGDS instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE);
+ $finish;
+ end
+
+ endcase
+
+
+ case (DIFF_TERM)
+
+ "TRUE", "FALSE" : ;
+ default : begin
+ $display("Attribute Syntax Error : The attribute DIFF_TERM on IBUFGDS instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DIFF_TERM);
+ $finish;
+ end
+
+ endcase
+
+
+ case (IBUF_DELAY_VALUE)
+
+ "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", "13", "14", "15", "16" : ;
+ default : begin
+ $display("Attribute Syntax Error : The attribute IBUF_DELAY_VALUE on IBUFGDS instance %m is set to %s. Legal values for this attribute are 0, 1, 2, ... or 16.", IBUF_DELAY_VALUE);
+ $finish;
+ end
+
+ endcase
+
+ end
+
+ always @(I or IB) begin
+ if (I == 1'b1 && IB == 1'b0)
+ o_out <= I;
+ else if (I == 1'b0 && IB == 1'b1)
+ o_out <= I;
+ else if (I == 1'bx && IB == 1'bx)
+ o_out <= 1'bx;
+ end
+
+endmodule
+
+