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-rw-r--r--usrp2/fifo/buffer_int2.v186
1 files changed, 97 insertions, 89 deletions
diff --git a/usrp2/fifo/buffer_int2.v b/usrp2/fifo/buffer_int2.v
index fab3ac314..e68f51e93 100644
--- a/usrp2/fifo/buffer_int2.v
+++ b/usrp2/fifo/buffer_int2.v
@@ -31,22 +31,23 @@ module buffer_int2
input rd_ready_i
);
- reg [BUF_SIZE-1:0] addr;
+ reg [BUF_SIZE-1:0] rd_addr, wr_addr;
wire [31:0] ctrl;
- wire we, en, done, error, idle, go;
-
- wire [BUF_SIZE-1:0] firstline = 0;
- wire [BUF_SIZE-1:0] lastline = ctrl[15+BUF_SIZE:16];
-
- wire read = ctrl[2];
- wire write = ctrl[1];
- wire clear = ctrl[0];
+ wire wr_done, wr_error, wr_idle;
+ wire rd_done, rd_error, rd_idle;
+ wire we, en, go;
+
+ reg [BUF_SIZE-1:0] lastline;
+ wire read = ctrl[3];
+ wire rd_clear = ctrl[2];
+ wire write = ctrl[1];
+ wire wr_clear = ctrl[0];
- reg [2:0] state;
- reg rd_sop, rd_eop;
- wire wr_sop, wr_eop, wr_error;
- reg [1:0] rd_occ;
- wire [1:0] wr_occ;
+ reg [2:0] rd_state, wr_state;
+ reg rd_sop, rd_eop;
+ wire wr_sop, wr_eop;
+ reg [1:0] rd_occ;
+ wire [1:0] wr_occ;
localparam IDLE = 3'd0;
localparam PRE_READ = 3'd1;
@@ -54,101 +55,107 @@ module buffer_int2
localparam WRITING = 3'd3;
localparam ERROR = 3'd4;
localparam DONE = 3'd5;
-
+
+ // read state machine
always @(posedge clk)
- if(rst)
+ if(rst | (rd_clear & go))
begin
- state <= IDLE;
+ rd_state <= IDLE;
rd_sop <= 0;
rd_eop <= 0;
rd_occ <= 0;
end
else
- if(clear)
- begin
- state <= IDLE;
- rd_sop <= 0;
- rd_eop <= 0;
- rd_occ <= 0;
- end
- else
- case(state)
- IDLE :
- if(go & read)
- begin
- addr <= firstline;
- state <= PRE_READ;
- end
- else if(go & write)
- begin
- addr <= firstline;
- state <= WRITING;
- end
-
- PRE_READ :
+ case(rd_state)
+ IDLE :
+ if(go & read)
begin
- state <= READING;
- addr <= addr + 1;
- rd_occ <= 2'b00;
- rd_sop <= 1;
- rd_eop <= 0;
+ rd_addr <= 0;
+ rd_state <= PRE_READ;
+ lastline <= ctrl[15+BUF_SIZE:16];
end
-
- READING :
- if(rd_ready_i)
- begin
- rd_sop <= 0;
- addr <= addr + 1;
- if(addr == lastline)
- begin
- rd_eop <= 1;
- // FIXME assign occ here
- rd_occ <= 0;
- end
- else
- rd_eop <= 0;
- if(rd_eop)
- state <= DONE;
- end
-
- WRITING :
+
+ PRE_READ :
+ begin
+ rd_state <= READING;
+ rd_addr <= rd_addr + 1;
+ rd_occ <= 2'b00;
+ rd_sop <= 1;
+ rd_eop <= 0;
+ end
+
+ READING :
+ if(rd_ready_i)
begin
- if(wr_ready_i)
+ rd_sop <= 0;
+ rd_addr <= rd_addr + 1;
+ if(rd_addr == lastline)
begin
- addr <= addr + 1;
- if(wr_error)
- begin
- state <= ERROR;
- // Save OCC flags here
- end
- else if((addr == lastline)||wr_eop)
- state <= DONE;
- end // if (wr_ready_i)
- end // case: WRITING
-
- endcase // case(state)
+ rd_eop <= 1;
+ // FIXME assign occ here
+ rd_occ <= 0;
+ end
+ else
+ rd_eop <= 0;
+ if(rd_eop)
+ rd_state <= DONE;
+ end
+
+ endcase // case(rd_state)
+
+ // write state machine
+ always @(posedge clk)
+ if(rst | wr_clear & go)
+ wr_state <= IDLE;
+ else
+ case(wr_state)
+ IDLE :
+ if(go & write)
+ begin
+ wr_addr <= 0;
+ wr_state <= WRITING;
+ end
+
+ WRITING :
+ if(wr_ready_i)
+ begin
+ wr_addr <= wr_addr + 1;
+ if(wr_sop & wr_eop)
+ wr_state <= ERROR; // Should save OCC flags here
+ else if(wr_eop)
+ wr_state <= DONE;
+ end // if (wr_ready_i)
+ endcase // case(wr_state)
assign rd_data_o[35:32] = { rd_occ[1:0], rd_eop, rd_sop };
- assign rd_ready_o = (state == READING);
+ assign rd_ready_o = (rd_state == READING);
assign wr_sop = wr_data_i[32];
assign wr_eop = wr_data_i[33];
assign wr_occ = wr_data_i[35:34];
- assign wr_error = wr_sop & wr_eop;
- assign wr_ready_o = (state == WRITING);
+ assign wr_ready_o = (wr_state == WRITING);
- assign we = (state == WRITING); // always write to avoid timing issue
- assign en = ~((state==READING)& ~rd_ready_i); // FIXME potential critical path
+ assign we = (wr_state == WRITING); // always write to avoid timing issue
+ assign en = ~((rd_state==READING)& ~rd_ready_i); // FIXME potential critical path
- assign done = (state == DONE);
- assign error = (state == ERROR);
- assign idle = (state == IDLE);
+ assign rd_done = (rd_state == DONE);
+ assign wr_done = (wr_state == DONE);
+ assign rd_error = (rd_state == ERROR);
+ assign wr_error = (wr_state == ERROR);
+ assign rd_idle = (rd_state == IDLE);
+ assign wr_idle = (wr_state == IDLE);
- ram_2port #(.DWIDTH(32),.AWIDTH(BUF_SIZE)) buffer
+ ram_2port #(.DWIDTH(32),.AWIDTH(BUF_SIZE)) buffer_in // CPU reads here
+ (.clka(wb_clk_i),.ena(wb_stb_i),.wea(1'b0),
+ .addra(wb_adr_i[BUF_SIZE+1:2]),.dia(0),.doa(wb_dat_o),
+ .clkb(clk),.enb(1'b1),.web(we),
+ .addrb(wr_addr),.dib(wr_data_i[31:0]),.dob());
+
+ ram_2port #(.DWIDTH(32),.AWIDTH(BUF_SIZE)) buffer_out // CPU writes here
(.clka(wb_clk_i),.ena(wb_stb_i),.wea(wb_we_i),
- .addra(wb_adr_i[BUF_SIZE+1:2]),.dia(wb_dat_i),.doa(wb_dat_o),
- .clkb(clk),.enb(en),.web(we),
- .addrb(addr),.dib(wr_data_i[31:0]),.dob(rd_data_o[31:0]));
+ .addra(wb_adr_i[BUF_SIZE+1:2]),.dia(wb_dat_i),.doa(),
+ .clkb(clk),.enb(en),.web(1'b0),
+ .addrb(rd_addr),.dib(0),.dob(rd_data_o[31:0]));
always @(posedge wb_clk_i)
if(wb_rst_i)
@@ -160,6 +167,7 @@ module buffer_int2
sreg(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),.in(set_data),
.out(ctrl),.changed(go));
- assign status = { {(16-BUF_SIZE){1'b0}},addr,8'b0,5'b0,idle,error,done};
+ assign status = { {(16-BUF_SIZE){1'b0}},wr_addr,
+ 8'b0,1'b0,rd_idle,rd_error,rd_done, 1'b0,wr_idle,wr_error,wr_done};
endmodule // buffer_int2
generated by cgit v1.2.3 (git 2.46.0) at 2025-10-31 06:10:03 +0000