diff options
Diffstat (limited to 'usrp2/control_lib/simple_spi_core.v')
| -rw-r--r-- | usrp2/control_lib/simple_spi_core.v | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/usrp2/control_lib/simple_spi_core.v b/usrp2/control_lib/simple_spi_core.v index 31bc26f95..208fceb23 100644 --- a/usrp2/control_lib/simple_spi_core.v +++ b/usrp2/control_lib/simple_spi_core.v @@ -166,9 +166,9 @@ module simple_spi_core CLK_REG: begin if (sclk_counter_done) begin state <= CLK_INV; - if (datain_edge != CLK_IDLE) datain_reg <= datain_next; - if (dataout_edge != CLK_IDLE) dataout_reg <= dataout_next; - sclk_reg <= ~CLK_IDLE; + if (datain_edge != CLK_IDLE) datain_reg <= datain_next; + if (dataout_edge != CLK_IDLE && bit_counter != 0) dataout_reg <= dataout_next; + sclk_reg <= ~CLK_IDLE; //transition to rising when CLK_IDLE == 0 end sclk_counter <= sclk_counter_next; end @@ -177,9 +177,9 @@ module simple_spi_core if (sclk_counter_done) begin state <= (bit_counter_done)? POST_IDLE : CLK_REG; bit_counter <= bit_counter_next; - if (datain_edge == CLK_IDLE) datain_reg <= datain_next; - if (dataout_edge == CLK_IDLE) dataout_reg <= dataout_next; - sclk_reg <= CLK_IDLE; + if (datain_edge == CLK_IDLE) datain_reg <= datain_next; + if (dataout_edge == CLK_IDLE && ~bit_counter_done) dataout_reg <= dataout_next; + sclk_reg <= CLK_IDLE; //transition to falling when CLK_IDLE == 0 end sclk_counter <= sclk_counter_next; end |