diff options
Diffstat (limited to 'simple_gemac/simple_gemac_wrapper.v')
| -rw-r--r-- | simple_gemac/simple_gemac_wrapper.v | 65 |
1 files changed, 57 insertions, 8 deletions
diff --git a/simple_gemac/simple_gemac_wrapper.v b/simple_gemac/simple_gemac_wrapper.v index cd586ae5d..e21eafb80 100644 --- a/simple_gemac/simple_gemac_wrapper.v +++ b/simple_gemac/simple_gemac_wrapper.v @@ -8,13 +8,10 @@ module simple_gemac_wrapper // Flow Control Interface input pause_req, input [15:0] pause_time, - // RX Client Interface - output rx_clk, output [7:0] rx_ll_data, output rx_ll_sof, output rx_ll_eof, - output rx_ll_error, output rx_ll_src_rdy, input rx_ll_dst_rdy, - - // TX Client Interface - output tx_clk, input [7:0] tx_ll_data, input tx_ll_sof, input tx_ll_eof, - input tx_ll_src_rdy, output tx_ll_dst_rdy, + // Client FIFO Interfaces + input sys_clk, + output [35:0] rx_f36_data, output rx_f36_src_rdy, input rx_f36_dst_rdy, + input [35:0] tx_f36_data, input tx_f36_src_rdy, output tx_f36_dst_rdy, // Wishbone Interface input wb_clk, input wb_rst, input wb_stb, input wb_cyc, output wb_ack, input wb_we, @@ -59,14 +56,66 @@ module simple_gemac_wrapper .pass_ucast(pass_ucast), .pass_mcast(pass_mcast), .pass_bcast(pass_bcast), .pass_pause(pass_pause), .pass_all(pass_all), .pause_en(pause_en) ); + // RX FIFO Chain + wire rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy; + wire rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2_n, rx_ll_dst_rdy2; + wire [7:0] rx_ll_data, rx_ll_data2; + wire [35:0] rx_f36_data_int1; + wire rx_f36_src_rdy_int1, rx_f36_dst_rdy_int1; + rxmac_to_ll8 rx_adapt (.clk(rx_clk), .reset(rx_reset), .clear(0), .rx_data(rx_data), .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack), .ll_data(rx_ll_data), .ll_sof(rx_ll_sof), .ll_eof(rx_ll_eof), .ll_error(rx_ll_error), .ll_src_rdy(rx_ll_src_rdy), .ll_dst_rdy(rx_ll_dst_rdy)); + + ll8_shortfifo rx_sfifo + (.clk(rx_clk), .reset(rx_reset), .clear(0), + .datain(rx_ll_data), .sof_i(rx_ll_sof), .eof_i(rx_ll_eof), + .error_i(rx_ll_error), .src_rdy_i(rx_ll_src_rdy), .dst_rdy_o(rx_ll_dst_rdy), + .dataout(rx_ll_data2), .sof_o(rx_ll_sof2), .eof_o(rx_ll_eof2), + .error_o(rx_ll_error2), .src_rdy_o(rx_ll_src_rdy2), .dst_rdy_i(~rx_ll_dst_rdy2_n)); + + ll8_to_fifo36 ll8_to_fifo36 + (.clk(rx_clk), .reset(rx_reset), .clear(0), + .ll_data(rx_ll_data2), .ll_sof_n(~rx_ll_sof2), .ll_eof_n(~rx_ll_eof2), + .ll_src_rdy_n(~rx_ll_src_rdy2), .ll_dst_rdy_n(rx_ll_dst_rdy2_n), + .f36_data(rx_f36_data_int1), .f36_src_rdy_o(rx_f36_src_rdy_int1), .f36_dst_rdy_i(rx_f36_dst_rdy_int1)); + + cascadefifo_2clock #(.DWIDTH(36), .AWIDTH(9)) rx_2clk_fifo + (.wclk(rx_clk), .datain(rx_f36_data_int1), + .src_rdy_i(rx_f36_src_rdy_int1), .dst_rdy_o(rx_f36_dst_rdy_int1), .level_wclk(), + .rclk(sys_clk), .dataout(rx_f36_data), + .src_rdy_o(rx_f36_src_rdy), .dst_rdy_i(rx_f36_dst_rdy), .level_rclk(), .arst(reset)); + + // TX FIFO Chain + wire tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy; + wire tx_ll_sof2, tx_ll_eof2, tx_ll_src_rdy2, tx_ll_dst_rdy2; + wire [7:0] tx_ll_data, tx_ll_data2; + wire [35:0] tx_f36_data_int1; + wire tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1; + + cascadefifo_2clock #(.DWIDTH(36), .AWIDTH(9)) tx_2clk_fifo + (.wclk(sys_clk), .datain(tx_f36_data), + .src_rdy_i(tx_f36_src_rdy), .dst_rdy_o(tx_f36_dst_rdy), .level_wclk(), + .rclk(tx_clk), .dataout(tx_f36_data_int1), + .src_rdy_o(tx_f36_src_rdy_int1), .dst_rdy_i(tx_f36_dst_rdy_int1), .level_rclk(), .arst(reset)); + + fifo36_to_ll8 fifo36_to_ll8 + (.clk(tx_clk), .reset(tx_reset), .clear(clear), + .f36_data(tx_f36_data_int1), .f36_src_rdy_i(tx_f36_src_rdy_int1), .f36_dst_rdy_o(tx_f36_dst_rdy_int1), + .ll_data(tx_ll_data2), .ll_sof_n(tx_ll_sof2_n), .ll_eof_n(tx_ll_eof2_n), + .ll_src_rdy_n(tx_ll_src_rdy2_n), .ll_dst_rdy_n(~tx_ll_dst_rdy2)); + + ll8_shortfifo tx_sfifo + (.clk(rx_clk), .reset(tx_reset), .clear(clear), + .datain(tx_ll_data2), .sof_i(tx_ll_sof2), .eof_i(tx_ll_eof2), + .error_i(0), .src_rdy_i(~tx_ll_src_rdy2_n), .dst_rdy_o(tx_ll_dst_rdy2), + .dataout(tx_ll_data), .sof_o(tx_ll_sof), .eof_o(tx_ll_eof), + .error_o(), .src_rdy_o(tx_ll_src_rdy), .dst_rdy_i(tx_ll_dst_rdy)); ll8_to_txmac ll8_to_txmac - (.clk(tx_clk), .reset(tx_reset), .clear(0), + (.clk(tx_clk), .reset(tx_reset), .clear(clear), .ll_data(tx_ll_data), .ll_sof(tx_ll_sof), .ll_eof(tx_ll_eof), .ll_src_rdy(tx_ll_src_rdy), .ll_dst_rdy(tx_ll_dst_rdy), .tx_data(tx_data), .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack)); |