diff options
Diffstat (limited to 'opencores/uart16550/sim')
70 files changed, 0 insertions, 555 deletions
diff --git a/opencores/uart16550/sim/CVS/Entries b/opencores/uart16550/sim/CVS/Entries deleted file mode 100644 index 178481050..000000000 --- a/opencores/uart16550/sim/CVS/Entries +++ /dev/null @@ -1 +0,0 @@ -D diff --git a/opencores/uart16550/sim/CVS/Entries.Log b/opencores/uart16550/sim/CVS/Entries.Log deleted file mode 100644 index 4677f5bea..000000000 --- a/opencores/uart16550/sim/CVS/Entries.Log +++ /dev/null @@ -1,2 +0,0 @@ -A D/gate_sim//// -A D/rtl_sim//// diff --git a/opencores/uart16550/sim/CVS/Repository b/opencores/uart16550/sim/CVS/Repository deleted file mode 100644 index 7a152b5d7..000000000 --- a/opencores/uart16550/sim/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -uart16550/sim diff --git a/opencores/uart16550/sim/CVS/Root b/opencores/uart16550/sim/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/uart16550/sim/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/uart16550/sim/CVS/Template b/opencores/uart16550/sim/CVS/Template deleted file mode 100644 index e69de29bb..000000000 --- a/opencores/uart16550/sim/CVS/Template +++ /dev/null diff --git a/opencores/uart16550/sim/gate_sim/CVS/Entries b/opencores/uart16550/sim/gate_sim/CVS/Entries deleted file mode 100644 index 178481050..000000000 --- a/opencores/uart16550/sim/gate_sim/CVS/Entries +++ /dev/null @@ -1 +0,0 @@ -D diff --git a/opencores/uart16550/sim/gate_sim/CVS/Entries.Log b/opencores/uart16550/sim/gate_sim/CVS/Entries.Log deleted file mode 100644 index 7a4fd3fe3..000000000 --- a/opencores/uart16550/sim/gate_sim/CVS/Entries.Log +++ /dev/null @@ -1,5 +0,0 @@ -A D/bin//// -A D/log//// -A D/out//// -A D/run//// -A D/src//// diff --git a/opencores/uart16550/sim/gate_sim/CVS/Repository b/opencores/uart16550/sim/gate_sim/CVS/Repository deleted file mode 100644 index 2717c3bbf..000000000 --- a/opencores/uart16550/sim/gate_sim/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -uart16550/sim/gate_sim diff --git a/opencores/uart16550/sim/gate_sim/CVS/Root b/opencores/uart16550/sim/gate_sim/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/uart16550/sim/gate_sim/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/uart16550/sim/gate_sim/CVS/Template b/opencores/uart16550/sim/gate_sim/CVS/Template deleted file mode 100644 index e69de29bb..000000000 --- a/opencores/uart16550/sim/gate_sim/CVS/Template +++ /dev/null diff --git a/opencores/uart16550/sim/gate_sim/bin/.keepme b/opencores/uart16550/sim/gate_sim/bin/.keepme deleted file mode 100644 index e69de29bb..000000000 --- a/opencores/uart16550/sim/gate_sim/bin/.keepme +++ /dev/null diff --git a/opencores/uart16550/sim/gate_sim/bin/CVS/Entries b/opencores/uart16550/sim/gate_sim/bin/CVS/Entries deleted file mode 100644 index 49302b141..000000000 --- a/opencores/uart16550/sim/gate_sim/bin/CVS/Entries +++ /dev/null @@ -1,2 +0,0 @@ -/.keepme/1.1/Sun Aug 12 18:52:53 2001// -D diff --git a/opencores/uart16550/sim/gate_sim/bin/CVS/Repository b/opencores/uart16550/sim/gate_sim/bin/CVS/Repository deleted file mode 100644 index 23fff6f04..000000000 --- a/opencores/uart16550/sim/gate_sim/bin/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -uart16550/sim/gate_sim/bin diff --git a/opencores/uart16550/sim/gate_sim/bin/CVS/Root b/opencores/uart16550/sim/gate_sim/bin/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/uart16550/sim/gate_sim/bin/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/uart16550/sim/gate_sim/bin/CVS/Template b/opencores/uart16550/sim/gate_sim/bin/CVS/Template deleted file mode 100644 index e69de29bb..000000000 --- a/opencores/uart16550/sim/gate_sim/bin/CVS/Template +++ /dev/null diff --git a/opencores/uart16550/sim/gate_sim/log/.keepme b/opencores/uart16550/sim/gate_sim/log/.keepme deleted file mode 100644 index e69de29bb..000000000 --- a/opencores/uart16550/sim/gate_sim/log/.keepme +++ /dev/null diff --git a/opencores/uart16550/sim/gate_sim/log/CVS/Entries b/opencores/uart16550/sim/gate_sim/log/CVS/Entries deleted file mode 100644 index c6b9be28c..000000000 --- a/opencores/uart16550/sim/gate_sim/log/CVS/Entries +++ /dev/null @@ -1,2 +0,0 @@ -/.keepme/1.1/Sun Aug 12 18:52:56 2001// -D diff --git a/opencores/uart16550/sim/gate_sim/log/CVS/Repository b/opencores/uart16550/sim/gate_sim/log/CVS/Repository deleted file mode 100644 index a59f7759d..000000000 --- a/opencores/uart16550/sim/gate_sim/log/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -uart16550/sim/gate_sim/log diff --git a/opencores/uart16550/sim/gate_sim/log/CVS/Root b/opencores/uart16550/sim/gate_sim/log/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/uart16550/sim/gate_sim/log/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/uart16550/sim/gate_sim/log/CVS/Template b/opencores/uart16550/sim/gate_sim/log/CVS/Template deleted file mode 100644 index e69de29bb..000000000 --- a/opencores/uart16550/sim/gate_sim/log/CVS/Template +++ /dev/null diff --git a/opencores/uart16550/sim/gate_sim/out/.keepme b/opencores/uart16550/sim/gate_sim/out/.keepme deleted file mode 100644 index e69de29bb..000000000 --- a/opencores/uart16550/sim/gate_sim/out/.keepme +++ /dev/null diff --git a/opencores/uart16550/sim/gate_sim/out/CVS/Entries b/opencores/uart16550/sim/gate_sim/out/CVS/Entries deleted file mode 100644 index ea09c9884..000000000 --- a/opencores/uart16550/sim/gate_sim/out/CVS/Entries +++ /dev/null @@ -1,2 +0,0 @@ -/.keepme/1.1/Sun Aug 12 18:52:58 2001// -D diff --git a/opencores/uart16550/sim/gate_sim/out/CVS/Repository b/opencores/uart16550/sim/gate_sim/out/CVS/Repository deleted file mode 100644 index 904082638..000000000 --- a/opencores/uart16550/sim/gate_sim/out/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -uart16550/sim/gate_sim/out diff --git a/opencores/uart16550/sim/gate_sim/out/CVS/Root b/opencores/uart16550/sim/gate_sim/out/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/uart16550/sim/gate_sim/out/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/uart16550/sim/gate_sim/out/CVS/Template b/opencores/uart16550/sim/gate_sim/out/CVS/Template deleted file mode 100644 index e69de29bb..000000000 --- a/opencores/uart16550/sim/gate_sim/out/CVS/Template +++ /dev/null diff --git a/opencores/uart16550/sim/gate_sim/run/.keepme b/opencores/uart16550/sim/gate_sim/run/.keepme deleted file mode 100644 index e69de29bb..000000000 --- a/opencores/uart16550/sim/gate_sim/run/.keepme +++ /dev/null diff --git a/opencores/uart16550/sim/gate_sim/run/CVS/Entries b/opencores/uart16550/sim/gate_sim/run/CVS/Entries deleted file mode 100644 index 170c5aa96..000000000 --- a/opencores/uart16550/sim/gate_sim/run/CVS/Entries +++ /dev/null @@ -1,2 +0,0 @@ -/.keepme/1.1/Sun Aug 12 18:52:59 2001// -D diff --git a/opencores/uart16550/sim/gate_sim/run/CVS/Repository b/opencores/uart16550/sim/gate_sim/run/CVS/Repository deleted file mode 100644 index f0fe74e8b..000000000 --- a/opencores/uart16550/sim/gate_sim/run/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -uart16550/sim/gate_sim/run diff --git a/opencores/uart16550/sim/gate_sim/run/CVS/Root b/opencores/uart16550/sim/gate_sim/run/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/uart16550/sim/gate_sim/run/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/uart16550/sim/gate_sim/run/CVS/Template b/opencores/uart16550/sim/gate_sim/run/CVS/Template deleted file mode 100644 index e69de29bb..000000000 --- a/opencores/uart16550/sim/gate_sim/run/CVS/Template +++ /dev/null diff --git a/opencores/uart16550/sim/gate_sim/src/.keepme b/opencores/uart16550/sim/gate_sim/src/.keepme deleted file mode 100644 index e69de29bb..000000000 --- a/opencores/uart16550/sim/gate_sim/src/.keepme +++ /dev/null diff --git a/opencores/uart16550/sim/gate_sim/src/CVS/Entries b/opencores/uart16550/sim/gate_sim/src/CVS/Entries deleted file mode 100644 index 76093103c..000000000 --- a/opencores/uart16550/sim/gate_sim/src/CVS/Entries +++ /dev/null @@ -1,2 +0,0 @@ -/.keepme/1.1/Sun Aug 12 18:53:01 2001// -D diff --git a/opencores/uart16550/sim/gate_sim/src/CVS/Repository b/opencores/uart16550/sim/gate_sim/src/CVS/Repository deleted file mode 100644 index e90e5de35..000000000 --- a/opencores/uart16550/sim/gate_sim/src/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -uart16550/sim/gate_sim/src diff --git a/opencores/uart16550/sim/gate_sim/src/CVS/Root b/opencores/uart16550/sim/gate_sim/src/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/uart16550/sim/gate_sim/src/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/uart16550/sim/gate_sim/src/CVS/Template b/opencores/uart16550/sim/gate_sim/src/CVS/Template deleted file mode 100644 index e69de29bb..000000000 --- a/opencores/uart16550/sim/gate_sim/src/CVS/Template +++ /dev/null diff --git a/opencores/uart16550/sim/rtl_sim/CVS/Entries b/opencores/uart16550/sim/rtl_sim/CVS/Entries deleted file mode 100644 index 178481050..000000000 --- a/opencores/uart16550/sim/rtl_sim/CVS/Entries +++ /dev/null @@ -1 +0,0 @@ -D diff --git a/opencores/uart16550/sim/rtl_sim/CVS/Entries.Log b/opencores/uart16550/sim/rtl_sim/CVS/Entries.Log deleted file mode 100644 index 7a4fd3fe3..000000000 --- a/opencores/uart16550/sim/rtl_sim/CVS/Entries.Log +++ /dev/null @@ -1,5 +0,0 @@ -A D/bin//// -A D/log//// -A D/out//// -A D/run//// -A D/src//// diff --git a/opencores/uart16550/sim/rtl_sim/CVS/Repository b/opencores/uart16550/sim/rtl_sim/CVS/Repository deleted file mode 100644 index 6880ade98..000000000 --- a/opencores/uart16550/sim/rtl_sim/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -uart16550/sim/rtl_sim diff --git a/opencores/uart16550/sim/rtl_sim/CVS/Root b/opencores/uart16550/sim/rtl_sim/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/uart16550/sim/rtl_sim/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/uart16550/sim/rtl_sim/CVS/Template b/opencores/uart16550/sim/rtl_sim/CVS/Template deleted file mode 100644 index e69de29bb..000000000 --- a/opencores/uart16550/sim/rtl_sim/CVS/Template +++ /dev/null diff --git a/opencores/uart16550/sim/rtl_sim/bin/CVS/Entries b/opencores/uart16550/sim/rtl_sim/bin/CVS/Entries deleted file mode 100644 index 4993d601c..000000000 --- a/opencores/uart16550/sim/rtl_sim/bin/CVS/Entries +++ /dev/null @@ -1,3 +0,0 @@ -/nc.scr/1.4/Mon Jul 29 21:15:18 2002/-kb/ -/sim.tcl/1.2/Mon Dec 3 21:44:29 2001/-kb/ -D diff --git a/opencores/uart16550/sim/rtl_sim/bin/CVS/Repository b/opencores/uart16550/sim/rtl_sim/bin/CVS/Repository deleted file mode 100644 index 1ea808f7b..000000000 --- a/opencores/uart16550/sim/rtl_sim/bin/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -uart16550/sim/rtl_sim/bin diff --git a/opencores/uart16550/sim/rtl_sim/bin/CVS/Root b/opencores/uart16550/sim/rtl_sim/bin/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/uart16550/sim/rtl_sim/bin/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/uart16550/sim/rtl_sim/bin/CVS/Template b/opencores/uart16550/sim/rtl_sim/bin/CVS/Template deleted file mode 100644 index e69de29bb..000000000 --- a/opencores/uart16550/sim/rtl_sim/bin/CVS/Template +++ /dev/null diff --git a/opencores/uart16550/sim/rtl_sim/bin/nc.scr b/opencores/uart16550/sim/rtl_sim/bin/nc.scr deleted file mode 100644 index c42e3c346..000000000 --- a/opencores/uart16550/sim/rtl_sim/bin/nc.scr +++ /dev/null @@ -1,9 +0,0 @@ -+libext+.v -+access+wr -+mess -+incdir+../../../rtl/verilog+../../../bench/verilog -+tcl+../bin/sim.tcl --y ../../../rtl/verilog --y ../../../bench/verilog -../../../bench/verilog/uart_test.v -//+gui diff --git a/opencores/uart16550/sim/rtl_sim/bin/sim.tcl b/opencores/uart16550/sim/rtl_sim/bin/sim.tcl deleted file mode 100644 index 18a0dbec4..000000000 --- a/opencores/uart16550/sim/rtl_sim/bin/sim.tcl +++ /dev/null @@ -1,5 +0,0 @@ -database -open waves -into ../out/uart -default -probe -create -shm uart_test -all -depth all -stop -create -time 1000000000ns -relative -run -quit diff --git a/opencores/uart16550/sim/rtl_sim/log/.keepme b/opencores/uart16550/sim/rtl_sim/log/.keepme deleted file mode 100644 index e69de29bb..000000000 --- a/opencores/uart16550/sim/rtl_sim/log/.keepme +++ /dev/null diff --git a/opencores/uart16550/sim/rtl_sim/log/CVS/Entries b/opencores/uart16550/sim/rtl_sim/log/CVS/Entries deleted file mode 100644 index 8a92af1b0..000000000 --- a/opencores/uart16550/sim/rtl_sim/log/CVS/Entries +++ /dev/null @@ -1,4 +0,0 @@ -/.keepme/1.1/Sun Aug 12 18:53:04 2001// -/uart_interrupts_report.log/1.1/Sat Mar 27 04:09:24 2004// -/uart_interrupts_verbose.log/1.1/Sat Mar 27 04:09:24 2004// -D diff --git a/opencores/uart16550/sim/rtl_sim/log/CVS/Repository b/opencores/uart16550/sim/rtl_sim/log/CVS/Repository deleted file mode 100644 index 61aafb858..000000000 --- a/opencores/uart16550/sim/rtl_sim/log/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -uart16550/sim/rtl_sim/log diff --git a/opencores/uart16550/sim/rtl_sim/log/CVS/Root b/opencores/uart16550/sim/rtl_sim/log/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/uart16550/sim/rtl_sim/log/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/uart16550/sim/rtl_sim/log/CVS/Template b/opencores/uart16550/sim/rtl_sim/log/CVS/Template deleted file mode 100644 index e69de29bb..000000000 --- a/opencores/uart16550/sim/rtl_sim/log/CVS/Template +++ /dev/null diff --git a/opencores/uart16550/sim/rtl_sim/log/uart_interrupts_report.log b/opencores/uart16550/sim/rtl_sim/log/uart_interrupts_report.log deleted file mode 100644 index 64b5c1887..000000000 --- a/opencores/uart16550/sim/rtl_sim/log/uart_interrupts_report.log +++ /dev/null @@ -1,23 +0,0 @@ -
----------------------------------------------------------------------------
-
-Initialization of UART.
- PASSED!
- Simulation Time: 621000
-
----------------------------------------------------------------------------
-
-Interrupt test.
- FAILED!
- Failure message: Bit 5 of LSR register not '1'!.
- Simulation Time: 5734521200
-
----------------------------------------------------------------------------
-
-TEST CASE execution summary:
-Number of tests PASSED=1
-Number of tests FAILED=1
- Simulation End Time: 5834521200
-
----------------------------------------------------------------------------
-
diff --git a/opencores/uart16550/sim/rtl_sim/log/uart_interrupts_verbose.log b/opencores/uart16550/sim/rtl_sim/log/uart_interrupts_verbose.log deleted file mode 100644 index 0382f36e0..000000000 --- a/opencores/uart16550/sim/rtl_sim/log/uart_interrupts_verbose.log +++ /dev/null @@ -1,104 +0,0 @@ -
----------------------------------------------------------------------------
-- Initialization of UART.
----------------------------------------------------------------------------
-
-Time: 200 (testbench_utilities.do_reset)
-*N, RESET signal asynchronously set.
-Time: 200 (testbench_utilities.disable_clk_generators)
-*N, Following clocks are DISABLED:
-Time: 200 (testbench_utilities.disable_clk_generators)
-*N, - WB_clk
-Time: 200 (testbench_utilities.disable_clk_generators)
-*N, - RX_clk
-Time: 200 (testbench_utilities.disable_clk_generators)
-*N, - TX_clk
-Time: 200 (testbench_utilities.disable_clk_generators)
-*N, - TX_clk_divided
-Time: 200 (testbench_utilities.set_device_tx_rx_clk_divisor)
-*N, UART DEVICE TX/RX clock divisor: 1000.
-Time: 200 (testbench_utilities.set_wb_clock_period)
-*N, WB & UART DEVICE TX/RX clock period: 64.
-Time: 200 (testbench_utilities.enable_clk_generators)
-*N, Following clocks are ENABLED:
-Time: 200 (testbench_utilities.enable_clk_generators)
-*N, - WB_clk
-Time: 200 (testbench_utilities.enable_clk_generators)
-*N, - RX_clk
-Time: 200 (testbench_utilities.enable_clk_generators)
-*N, - TX_clk
-Time: 200 (testbench_utilities.enable_clk_generators)
-*N, - TX_clk_divided
-Time: 11100 (testbench_utilities.release_reset)
-*N, RESET signal released synchronously to WB clk.
-Time: 11100 (uart_wb_utilities.write_dlr)
-*N, DLAB in LC Register is going to be 1.
-Time: 11100 (uart_wb_utilities.write_dlr)
-*N, Current LCR = 3.
-Time: 11100 (uart_wb_utilities.write_lcr)
-*N, WRITING UART's LC Register.
-Time: 101000 (uart_wb_utilities.write_lcr)
-*N, Write LCR = 83.
-Time: 101000 (uart_wb_utilities.write_dlr)
-*N, WRITING UART's DL Register [15:8].
-Time: 161000 (uart_wb_utilities.write_dlr)
-*N, Write DLR [15:8] = 10.
-Time: 161000 (uart_wb_utilities.write_dlr)
-*N, WRITING UART's DL Register [ 7:0].
-Time: 281000 (uart_wb_utilities.write_dlr)
-*N, Write DLR [ 7:0] = 0.
-Time: 281000 (uart_wb_utilities.write_dlr)
-*N, DLAB in LC Register is going to be 0.
-Time: 281000 (uart_wb_utilities.write_lcr)
-*N, WRITING UART's LC Register.
-Time: 371000 (uart_wb_utilities.write_lcr)
-*N, Write LCR = 3.
-Time: 371000 (uart_wb_utilities.write_ier)
-*N, WRITING UART's IE Register.
-Time: 411000 (uart_wb_utilities.write_ier)
-*N, Write IER = 7.
-Time: 411000 (uart_wb_utilities.write_fcr)
-*N, WRITING UART's FC Register.
-Time: 511000 (uart_wb_utilities.write_fcr)
-*N, Write FCR = c0.
-Time: 511000 (uart_wb_utilities.write_lcr)
-*N, WRITING UART's LC Register.
-Time: 621000 (uart_wb_utilities.write_lcr)
-*N, Write LCR = 3.
-Time: 621000 (uart_device_utilities.set_rx_length)
-*N, SETTING RX CHAR length.
-Time: 621000 (uart_device_utilities.set_rx_length)
-*N, Length: 8.
-Time: 621000 (uart_device_utilities.disable_rx_parity)
-*N, DISABLING RX CHAR parity.
-Time: 621000 (uart_device_utilities.set_rx_second_stop_bit)
-*N, SETTING RX CHAR 1 stop bit.
-Time: 621000 (uart_device_utilities.set_tx_length)
-*N, SETTING TX CHAR length.
-Time: 621000 (uart_device_utilities.set_tx_length)
-*N, Length: 8.
-Time: 621000 (uart_device_utilities.disable_tx_parity)
-*N, DISABLING TX CHAR parity.
-Time: 621000 (uart_device_utilities.correct_tx_parity)
-*N, DISABLING WRONG parity generation.
-Time: 621000 (uart_device_utilities.correct_tx_frame)
-*N, DISABLING WRONG frame generation.
-Time: 621000 (uart_device_utilities.generate_tx_glitch)
-*N, DISABLING 1 TIME glitch generation with CLKs delay.
-Time: 621000 (uart_device_utilities.generate_tx_glitch)
-*N, CLKs delay from start bit edge: 0.
-
----------------------------------------------------------------------------
-- Interrupt test.
----------------------------------------------------------------------------
-
-Time: 621000 (testbench_utilities.wait_for_num_of_wb_clk)
-*N, Waiting for following number of WB CLK periods:
-Time: 621000 (testbench_utilities.wait_for_num_of_wb_clk)
-*N, Waiting for following number of WB CLK periods: 450000.
-Time: 701000 (uart_wb_utilities.write_char)
-*N, Write TRR = aa.
-Time: 5734501000 (testbench.write_tx_shift_reg_read_tx_fifo)
-*N, TX FIFO is empty!
-Time: 5734521200 (testbench.tx_fifo_status_changing)
-*E, Bit 5 of LSR register not '1'!
diff --git a/opencores/uart16550/sim/rtl_sim/out/.keepme b/opencores/uart16550/sim/rtl_sim/out/.keepme deleted file mode 100644 index e69de29bb..000000000 --- a/opencores/uart16550/sim/rtl_sim/out/.keepme +++ /dev/null diff --git a/opencores/uart16550/sim/rtl_sim/out/CVS/Entries b/opencores/uart16550/sim/rtl_sim/out/CVS/Entries deleted file mode 100644 index b974d3668..000000000 --- a/opencores/uart16550/sim/rtl_sim/out/CVS/Entries +++ /dev/null @@ -1,2 +0,0 @@ -/.keepme/1.1/Sun Aug 12 18:53:06 2001// -D diff --git a/opencores/uart16550/sim/rtl_sim/out/CVS/Repository b/opencores/uart16550/sim/rtl_sim/out/CVS/Repository deleted file mode 100644 index e52a5c283..000000000 --- a/opencores/uart16550/sim/rtl_sim/out/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -uart16550/sim/rtl_sim/out diff --git a/opencores/uart16550/sim/rtl_sim/out/CVS/Root b/opencores/uart16550/sim/rtl_sim/out/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/uart16550/sim/rtl_sim/out/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/uart16550/sim/rtl_sim/out/CVS/Template b/opencores/uart16550/sim/rtl_sim/out/CVS/Template deleted file mode 100644 index e69de29bb..000000000 --- a/opencores/uart16550/sim/rtl_sim/out/CVS/Template +++ /dev/null diff --git a/opencores/uart16550/sim/rtl_sim/run/CVS/Entries b/opencores/uart16550/sim/rtl_sim/run/CVS/Entries deleted file mode 100644 index 0f0e80b14..000000000 --- a/opencores/uart16550/sim/rtl_sim/run/CVS/Entries +++ /dev/null @@ -1,4 +0,0 @@ -/run_signalscan/1.1.1.1/Sun Aug 12 16:27:51 2001/-kb/ -/run_sim/1.1.1.1/Sun Aug 12 16:27:51 2001/-kb/ -/run_sim.scr/1.1/Sat Mar 27 04:07:47 2004// -D diff --git a/opencores/uart16550/sim/rtl_sim/run/CVS/Repository b/opencores/uart16550/sim/rtl_sim/run/CVS/Repository deleted file mode 100644 index 6dea2247d..000000000 --- a/opencores/uart16550/sim/rtl_sim/run/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -uart16550/sim/rtl_sim/run diff --git a/opencores/uart16550/sim/rtl_sim/run/CVS/Root b/opencores/uart16550/sim/rtl_sim/run/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/uart16550/sim/rtl_sim/run/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/uart16550/sim/rtl_sim/run/CVS/Template b/opencores/uart16550/sim/rtl_sim/run/CVS/Template deleted file mode 100644 index e69de29bb..000000000 --- a/opencores/uart16550/sim/rtl_sim/run/CVS/Template +++ /dev/null diff --git a/opencores/uart16550/sim/rtl_sim/run/run_signalscan b/opencores/uart16550/sim/rtl_sim/run/run_signalscan deleted file mode 100755 index cd6536563..000000000 --- a/opencores/uart16550/sim/rtl_sim/run/run_signalscan +++ /dev/null @@ -1,2 +0,0 @@ -signalscan ../out/uart/uart.trn & -# -do ../out/uart/uart.do & diff --git a/opencores/uart16550/sim/rtl_sim/run/run_sim b/opencores/uart16550/sim/rtl_sim/run/run_sim deleted file mode 100755 index f86c2f9b5..000000000 --- a/opencores/uart16550/sim/rtl_sim/run/run_sim +++ /dev/null @@ -1 +0,0 @@ -ncverilog -f ../bin/nc.scr & diff --git a/opencores/uart16550/sim/rtl_sim/run/run_sim.scr b/opencores/uart16550/sim/rtl_sim/run/run_sim.scr deleted file mode 100644 index 6bc0c5eec..000000000 --- a/opencores/uart16550/sim/rtl_sim/run/run_sim.scr +++ /dev/null @@ -1,345 +0,0 @@ -#!/bin/csh -f - - -# GLOBAL VARIABLES -################### - -set sim_top = testbench; -set arg_tool = "NCSim"; # By default NCSim is used as simulation tool -set arg_wave = 0; # By default waveform is not recorded -set arg_verb = 0; # By default basic display on monitor (no verbose) -set arg_test = 0; # By default all testcases are simulated - - -# GETTING PARAMETERS FROM COMMAND LINE -####################################### - -set cur_arg = 1; - -if ($#argv < 1) then - echo "" - echo " Verification without any argument:" -else - - while ($cur_arg <= $#argv) - - switch ("$argv[$cur_arg]") - # HELP ARGUMENT - case "-h": - goto help - breaksw - case "help": - goto help - breaksw - # TOOL ARGUMENT - case "-m": - set arg_tool = "ModelSim"; - echo " $argv[$cur_arg] - ModelSim tool" - breaksw - case "modelsim" - set arg_tool = "ModelSim"; - echo " $argv[$cur_arg] - ModelSim tool" - breaksw - # WAVEFORM ARGUMENT - case "-w": - @ arg_wave = 1; - echo " $argv[$cur_arg] - Waveform" - breaksw - case "waveform": - @ arg_wave = 1; - echo " $argv[$cur_arg] - Waveform" - breaksw - # VERBOSE ARGUMENT - case "-v": - @ arg_verb = 1; - echo " $argv[$cur_arg] - Verbose" - breaksw - case "verbose": - @ arg_verb = 1; - echo " $argv[$cur_arg] - Verbose" - breaksw - # TESTCASE ARGUMENT - default: - if (-e ../../../bench/verilog/testcases/$argv[$cur_arg].v) then - set arg_test = $argv[$cur_arg]; - echo " $argv[$cur_arg] - Testcase" - # INVALID ARGUMENT - else - echo "" - echo " Invalid verification argument: $argv[$cur_arg]" - goto help - endif - breaksw - endsw - - @ cur_arg++ - end - -endif - - -# SIMULATION LOOP -################## - -set cur_test_num = 0; - -simulate: - - - # DELETING FILES - ################# - - # Prepared files - if (-e ./file_list.lst) then - rm -rf ./file_list.lst - endif - if (-e ../bin/cds.lib) then - rm -rf ../bin/cds.lib - endif - if (-e ../bin/hdl.var) then - rm -rf ../bin/hdl.var - endif - if (-e ./compile.args) then - rm -rf ./compile.args - endif - if (-e ./elab.args) then - rm -rf ./elab.args - endif - if (-e ./sim.args) then - rm -rf ./sim.args - endif - if (-e ./sim.tcl) then - rm -rf ./sim.tcl - endif - if (-e ./sim.do) then - rm -rf ./sim.do - endif - - # Projects, Libraries and Logs - if (-e ./uart.mpf) then - rm -rf ./uart.mpf - endif - if (-e ./work) then - rm -rf ./work - endif - if (-e ./INCA_libs/worklib) then - rm -rf ./INCA_libs/worklib - endif - - - # PREPARING FILE LIST - ###################### - - # Design files - echo "../../../rtl/verilog/uart_top.v" >> ./file_list.lst - echo "../../../rtl/verilog/uart_wb.v" >> ./file_list.lst - echo "../../../rtl/verilog/uart_transmitter.v" >> ./file_list.lst - echo "../../../rtl/verilog/uart_receiver.v" >> ./file_list.lst - echo "../../../rtl/verilog/uart_tfifo.v" >> ./file_list.lst - echo "../../../rtl/verilog/uart_rfifo.v" >> ./file_list.lst - echo "../../../rtl/verilog/uart_regs.v" >> ./file_list.lst - echo "../../../rtl/verilog/uart_debug_if.v" >> ./file_list.lst - - # Testcase file - if ($arg_test == 0) then - set i = 0; - foreach testcase (../../../bench/verilog/testcases/uart*.v) - if ($i == $cur_test_num) then - set testcase_i = $testcase:t:r - endif - @ i++ - end - set max_test_num = $i; - else - set testcase_i = $arg_test; - set max_test_num = 1; - endif - echo "//////////////////////////////////////////////////" > ./file_list.lst - echo "// File created within script ${0}" >> ./file_list.lst - echo "// path: $cwd" >> ./file_list.lst - echo "// user: $user" >> ./file_list.lst - echo "//////////////////////////////////////////////////" >> ./file_list.lst - echo "../../../bench/verilog/testcases/$testcase_i.v" >> ./file_list.lst - # Delete vawe out file for this testcase, if it already exists - if (-e ../out/$testcase_i.wlf) then - rm -rf ../out/$testcase_i.wlf - endif - # Delete log out file for this testcase, if it already exists - if (-e ../log/$testcase_i.log) then - rm -rf ../log/$testcase_i.log - endif - - # Testbench files - echo "../../../bench/verilog/uart_testbench.v" >> ./file_list.lst - echo "../../../bench/verilog/wb_master_model.v" >> ./file_list.lst - echo "../../../bench/verilog/uart_device.v" >> ./file_list.lst - echo "../../../bench/verilog/uart_testbench_utilities.v" >> ./file_list.lst - echo "../../../bench/verilog/uart_wb_utilities.v" >> ./file_list.lst - echo "../../../bench/verilog/uart_device_utilities.v" >> ./file_list.lst - - - # COMPILING & ELABORATING - ########################## - - if ("$arg_tool" == "NCSim") then - - # cds.lib library file - echo "//////////////////////////////////////////////////" > ../bin/cds.lib - echo "// File created within script ${0}" >> ../bin/cds.lib - echo "// path: $cwd" >> ../bin/cds.lib - echo "// user: $0" >> ../bin/cds.lib - echo "//////////////////////////////////////////////////" >> ../bin/cds.lib - echo "DEFINE worklib ./INCA_libs/worklib" >> ../bin/cds.lib - - # hdl.var variable file - echo "//////////////////////////////////////////////////" > ../bin/hdl.var - echo "// File created within script ${0}" >> ../bin/hdl.var - echo "// path: $cwd" >> ../bin/hdl.var - echo "// user: $0" >> ../bin/hdl.var - echo "//////////////////////////////////////////////////" >> ../bin/hdl.var - echo "INCLUDE \$CDS_INST_DIR/tools/inca/files/hdl.var" >> ../bin/hdl.var - echo "DEFINE WORK worklib" >> ../bin/hdl.var - - # compile.args argument file - echo "//////////////////////////////////////////////////" > ./compile.args - echo "// File created within script ${0}" >> ./compile.args - echo "// path: $cwd" >> ./compile.args - echo "// user: $0" >> ./compile.args - echo "//////////////////////////////////////////////////" >> ./compile.args - echo "-CDSLIB ../bin/cds.lib" >> ./compile.args - echo "-HDLVAR ../bin/hdl.var" >> ./compile.args - echo "-MESSAGES" >> ./compile.args - echo "-NOCOPYRIGHT" >> ./compile.args - echo "-INCDIR ../../../rtl/verilog" >> ./compile.args - echo "-INCDIR ../../../bench/verilog" >> ./compile.args - echo "-INCDIR ../../../bench/verilog/testcases" >> ./compile.args - if ($arg_verb == 1) then - echo "-DEFINE VERBOSE" >> ./compile.args - endif - cat ./file_list.lst >> ./compile.args - - # compiling - ncvlog -LOGFILE ../log/$testcase_i.compile.log -f ./compile.args #> /dev/null - - # elab.args argument file - echo "//////////////////////////////////////////////////" > ./elab.args - echo "// File created within script ${0}" >> ./elab.args - echo "// path: $cwd" >> ./elab.args - echo "// user: $0" >> ./elab.args - echo "//////////////////////////////////////////////////" >> ./elab.args - echo "-CDSLIB ../bin/cds.lib" >> ./elab.args - echo "-HDLVAR ../bin/hdl.var" >> ./elab.args - echo "-MESSAGES" >> ./elab.args - echo "-NOCOPYRIGHT" >> ./elab.args - echo "-NOTIMINGCHECKS" >> ./elab.args - echo "-SNAPSHOT worklib.testbench:rtl" >> ./elab.args - echo "-NO_TCHK_MSG" >> ./elab.args - echo "-ACCESS +RWC" >> ./elab.args - echo "worklib.$sim_top" >> ./elab.args - - # elaborating - ncelab -LOGFILE ../log/$testcase_i.elab.log -f ./elab.args #> /dev/null - else - - # compile.args argument file - echo "+libext+.v" >> ./compile.args - echo "-y ../../../rtl/verilog" >> ./compile.args - echo "-y ../../../bench/verilog" >> ./compile.args - echo "-y ../../../bench/verilog/testcases" >> ./compile.args - echo "-work ./work" >> ./compile.args - echo "+incdir+../../../rtl/verilog" >> ./compile.args - echo "+incdir+../../../bench/verilog" >> ./compile.args - echo '+define+LOG_DIR=\"../log/$testcase_i\"' >> ./compile.args - if ($arg_verb == 1) then - echo "+define+VERBOSE" >> ./compile.args - endif - cat ./file_list.lst >> ./compile.args - - # open project -# echo "project new ./ testbench ./work" >> ./sim.do - vlib -dos ./work - - # compiling - # echo "vlog -f ./compile.args" >> ./sim.do - vlog -f ./compile.args - endif - - - # SIMULATING - ############# - - if ("$arg_tool" == "NCSim") then - - # sim.args argument file - echo "//////////////////////////////////////////////////" > ./sim.args - echo "// File created within script ${0}" >> ./sim.args - echo "// path: $cwd" >> ./sim.args - echo "// user: $0" >> ./sim.args - echo "//////////////////////////////////////////////////" >> ./sim.args - echo "-CDSLIB ../bin/cds.lib" >> ./sim.args - echo "-HDLVAR ../bin/hdl.var" >> ./sim.args - echo "-MESSAGES" >> ./sim.args - echo "-NOCOPYRIGHT" >> ./sim.args - echo "-INPUT ./sim.tcl" >> ./sim.args - echo "worklib.testbench:rtl" >> ./sim.args - - # sim.tcl file - echo "//////////////////////////////////////////////////" > ./sim.tcl - echo "// File created within script ${0}" >> ./sim.tcl - echo "// path: $cwd" >> ./sim.tcl - echo "// user: $0" >> ./sim.tcl - echo "//////////////////////////////////////////////////" >> ./sim.tcl - if ($arg_wave) then - echo "database -open waves -shm -into ../out/waves.shm" >> ./sim.tcl - echo "probe -create -database waves $sim_top -shm -all -depth all" >> ./sim.tcl - echo "run" >> ./sim.tcl - else - echo "run" >> ./sim.tcl - endif - echo "quit" >> ./sim.tcl - - # simulating - ncsim -LICQUEUE -LOGFILE ../log/$testcase_i.sim.log -f ./sim.args - else - - # sim.do do file - echo "vsim work.testbench work.testbench_utilities work.uart_wb_utilities work.uart_device_utilities work.testcase -wlf ../out/$testcase_i.wlf" >> ./sim.do - if ($arg_wave) then - echo "log -r -internal -ports /testbench/*" >> ./sim.do - endif - echo "run -all" >> ./sim.do - - vsim -c -do ./sim.do - - endif - - @ cur_test_num++ - - if ($cur_test_num < $max_test_num) then - goto simulate - endif - -exit - - -# HELP DISPLAY -############### - -help: - echo "" - echo " Valid verification arguments:" - echo " 'help' / '-h' : This help is displayed" - echo " 'modelsim' / '-m' : ModelSim simulation tool is used, otherwise" - echo " NCSim is used (default)" - echo " 'waveform' / '-w' : Waveform output is recorded, otherwise" - echo " NO waveform is recorded (default)" - echo " 'verbose' / '-v' : Verbose display on monitor, otherwise" - echo " basic display on monitor (default)" - echo " '\042testcase\042' : Testcase which is going to be simulated, otherwise" - echo " ALL testcases are simulated - regression (default);" - echo " Available testcases:" - foreach testcase (../../../bench/verilog/testcases/uart*.v) - echo " "$testcase:t:r - end - echo "" -exit diff --git a/opencores/uart16550/sim/rtl_sim/src/.keepme b/opencores/uart16550/sim/rtl_sim/src/.keepme deleted file mode 100644 index e69de29bb..000000000 --- a/opencores/uart16550/sim/rtl_sim/src/.keepme +++ /dev/null diff --git a/opencores/uart16550/sim/rtl_sim/src/CVS/Entries b/opencores/uart16550/sim/rtl_sim/src/CVS/Entries deleted file mode 100644 index b974d3668..000000000 --- a/opencores/uart16550/sim/rtl_sim/src/CVS/Entries +++ /dev/null @@ -1,2 +0,0 @@ -/.keepme/1.1/Sun Aug 12 18:53:06 2001// -D diff --git a/opencores/uart16550/sim/rtl_sim/src/CVS/Repository b/opencores/uart16550/sim/rtl_sim/src/CVS/Repository deleted file mode 100644 index 8c096f117..000000000 --- a/opencores/uart16550/sim/rtl_sim/src/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -uart16550/sim/rtl_sim/src diff --git a/opencores/uart16550/sim/rtl_sim/src/CVS/Root b/opencores/uart16550/sim/rtl_sim/src/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/opencores/uart16550/sim/rtl_sim/src/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/uart16550/sim/rtl_sim/src/CVS/Template b/opencores/uart16550/sim/rtl_sim/src/CVS/Template deleted file mode 100644 index e69de29bb..000000000 --- a/opencores/uart16550/sim/rtl_sim/src/CVS/Template +++ /dev/null |