1 files changed, 0 insertions, 86 deletions
diff --git a/opencores/ethernet_tri_mode/syn/syn.prj b/opencores/ethernet_tri_mode/syn/syn.prj
deleted file mode 100644
index 568a7a4ed..000000000
--- a/opencores/ethernet_tri_mode/syn/syn.prj
+++ /dev/null
@@ -1,86 +0,0 @@
-#-- Synplicity, Inc.
-#-- Version Synplify 8.1
-#-- Project file D:\root\home\ethernet_tri_mode\syn\syn.prj
-#-- Written on Thu Jan 19 20:25:55 2006
-
-
-#add_file options
-add_file -verilog "../rtl/verilog/header.v"
-add_file -verilog "../rtl/verilog/MAC_tx/MAC_tx_FF.v"
-add_file -verilog "../rtl/verilog/MAC_tx/Ramdon_gen.v"
-add_file -verilog "../rtl/verilog/MAC_tx/CRC_gen.v"
-add_file -verilog "../rtl/verilog/MAC_tx/MAC_tx_addr_add.v"
-add_file -verilog "../rtl/verilog/MAC_tx/MAC_tx_Ctrl.v"
-add_file -verilog "../rtl/verilog/MAC_tx/flow_ctrl.v"
-add_file -verilog "../rtl/verilog/MAC_rx/CRC_chk.v"
-add_file -verilog "../rtl/verilog/MAC_rx/MAC_rx_add_chk.v"
-add_file -verilog "../rtl/verilog/MAC_rx/MAC_rx_FF.v"
-add_file -verilog "../rtl/verilog/MAC_rx/MAC_rx_ctrl.v"
-add_file -verilog "../rtl/verilog/RMON/RMON_addr_gen.v"
-add_file -verilog "../rtl/verilog/RMON/RMON_ctrl.v"
-add_file -verilog "../rtl/verilog/RMON/RMON_dpram.v"
-add_file -verilog "../rtl/verilog/MAC_rx/Broadcast_filter.v"
-add_file -verilog "../rtl/verilog/TECH/duram.v"
-add_file -verilog "../rtl/verilog/RMON.v"
-add_file -verilog "../rtl/verilog/MAC_rx.v"
-add_file -verilog "../rtl/verilog/MAC_tx.v"
-add_file -verilog "../rtl/verilog/miim/eth_clockgen.v"
-add_file -verilog "../rtl/verilog/miim/eth_outputcontrol.v"
-add_file -verilog "../rtl/verilog/miim/eth_shiftreg.v"
-add_file -verilog "../rtl/verilog/miim/timescale.v"
-add_file -verilog "../rtl/verilog/TECH/CLK_SWITCH.v"
-add_file -verilog "../rtl/verilog/TECH/CLK_DIV2.v"
-add_file -verilog "../rtl/verilog/eth_miim.v"
-add_file -verilog "../rtl/verilog/Clk_ctrl.v"
-add_file -verilog "../rtl/verilog/Phy_int.v"
-add_file -verilog "../rtl/verilog/Reg_int.v"
-add_file -verilog "../rtl/verilog/MAC_top.v"
-
-
-#implementation: "syn"
-impl -add syn
-
-#device options
-set_option -technology STRATIX
-set_option -part EP1S10
-set_option -package FC780
-set_option -speed_grade -5
-
-#compilation/mapping options
-set_option -default_enum_encoding onehot
-set_option -symbolic_fsm_compiler 0
-set_option -resource_sharing 1
-set_option -use_fsm_explorer 0
-
-#map options
-set_option -frequency auto
-set_option -run_prop_extract 0
-set_option -fanout_limit 500
-set_option -disable_io_insertion 0
-set_option -pipe 1
-set_option -update_models_cp 0
-set_option -retiming 0
-set_option -verification_mode 0
-set_option -fixgatedclocks 0
-set_option -no_sequential_opt 0
-
-#simulation options
-set_option -write_verilog 1
-set_option -write_vhdl 0
-
-#automatic place and route (vendor) options
-set_option -write_apr_constraint 0
-
-#set result format/file last
-project -result_file "./MAC_top.vqm"
-
-#
-#implementation attributes
-
-set_option -vlog_std v2001
-set_option -project_relative_includes 1
-
-#par_1 attributes
-set_option -job par_1 -add par
-set_option -job par_1 -option run_backannotation 0
-impl -active "syn"