diff options
Diffstat (limited to 'mpm/python/usrp_mpm/periph_manager/n3xx_periphs.py')
| -rw-r--r-- | mpm/python/usrp_mpm/periph_manager/n3xx_periphs.py | 144 |
1 files changed, 15 insertions, 129 deletions
diff --git a/mpm/python/usrp_mpm/periph_manager/n3xx_periphs.py b/mpm/python/usrp_mpm/periph_manager/n3xx_periphs.py index 9b83816c4..ef2372e62 100644 --- a/mpm/python/usrp_mpm/periph_manager/n3xx_periphs.py +++ b/mpm/python/usrp_mpm/periph_manager/n3xx_periphs.py @@ -1,5 +1,6 @@ # # Copyright 2018 Ettus Research, a National Instruments Company +# Copyright 2019 Ettus Research, a National Instruments Brand # # SPDX-License-Identifier: GPL-3.0-or-later # @@ -7,12 +8,11 @@ N3xx peripherals """ -import datetime from usrp_mpm import lib from usrp_mpm.sys_utils.sysfs_gpio import SysFSGPIO, GPIOBank -from usrp_mpm.sys_utils.uio import UIO from usrp_mpm.sys_utils import i2c_dev from usrp_mpm.chips.ds125df410 import DS125DF410 +from usrp_mpm.periph_manager.common import MboardRegsCommon # Map register values to SFP transport types N3XX_SFP_TYPES = { @@ -160,41 +160,20 @@ class BackpanelGPIO(GPIOBank): 0x7, # ddr ) -class MboardRegsControl(object): +class MboardRegsControl(MboardRegsCommon): """ Control the FPGA Motherboard registers """ - # Motherboard registers - MB_COMPAT_NUM = 0x0000 - MB_DATESTAMP = 0x0004 - MB_GIT_HASH = 0x0008 - MB_SCRATCH = 0x000C - MB_DEVICE_ID = 0x0010 - MB_RFNOC_INFO = 0x0014 - MB_CLOCK_CTRL = 0x0018 - MB_XADC_RB = 0x001C - MB_BUS_CLK_RATE = 0x0020 - MB_BUS_COUNTER = 0x0024 - MB_SFP0_INFO = 0x0028 - MB_SFP1_INFO = 0x002C - MB_GPIO_MASTER = 0x0030 - MB_GPIO_RADIO_SRC = 0x0034 - MB_NUM_TIMEKEEPERS = 0x0048 - # Timekeeper registers - MB_TIME_NOW_LO = 0x1000 - MB_TIME_NOW_HI = 0x1004 - MB_TIME_EVENT_LO = 0x1008 - MB_TIME_EVENT_HI = 0x100C - MB_TIME_CTRL = 0x1010 - MB_TIME_LAST_PPS_LO = 0x1014 - MB_TIME_LAST_PPS_HI = 0x1018 - MB_TIME_BASE_PERIOD_LO = 0x101C - MB_TIME_BASE_PERIOD_HI = 0x1020 - MB_TIMEKEEPER_OFFSET = 12 - - # Bitfield locations for the MB_RFNOC_INFO register. - MB_RFNOC_INFO_PROTO_VER = 0 - MB_RFNOC_INFO_CHDR_WIDTH = 16 + # pylint: disable=bad-whitespace + # Motherboard registers (on top of the ones in MboardRegsCommon) + MB_CLOCK_CTRL = 0x0018 + MB_XADC_RB = 0x001C + MB_BUS_CLK_RATE = 0x0020 + MB_BUS_COUNTER = 0x0024 + MB_SFP0_INFO = 0x0028 + MB_SFP1_INFO = 0x002C + MB_GPIO_MASTER = 0x0030 + MB_GPIO_RADIO_SRC = 0x0034 # Bitfield locations for the MB_CLOCK_CTRL register. MB_CLOCK_CTRL_PPS_SEL_INT_10 = 0 # pps_sel is one-hot encoded! @@ -207,66 +186,10 @@ class MboardRegsControl(object): MB_CLOCK_CTRL_MEAS_CLK_RESET = 12 # set to 1 to reset mmcm, default is 0 MB_CLOCK_CTRL_MEAS_CLK_LOCKED = 13 # locked indication for meas_clk mmcm MB_CLOCK_CTRL_DISABLE_REF_CLK = 16 # to disable the ref_clk, write a '1' + # pylint: enable=bad-whitespace def __init__(self, label, log): - self.log = log - self.regs = UIO( - label=label, - read_only=False - ) - self.poke32 = self.regs.poke32 - self.peek32 = self.regs.peek32 - - def get_compat_number(self): - """get FPGA compat number - - This function reads back FPGA compat number. - The return is a tuple of - 2 numbers: (major compat number, minor compat number ) - """ - with self.regs: - compat_number = self.peek32(self.MB_COMPAT_NUM) - minor = compat_number & 0xff - major = (compat_number>>16) & 0xff - return (major, minor) - - def set_device_id(self, device_id): - """ - Set device ID - """ - with self.regs: - self.log.trace("Writing MB_DEVICE_ID with 0x{:08X}".format(device_id)) - return self.poke32(self.MB_DEVICE_ID, device_id) - - def get_device_id(self): - """ - Get device ID - """ - with self.regs: - reg_val = self.peek32(self.MB_DEVICE_ID) - device_id = reg_val & 0x0000ffff - self.log.trace("Read MB_DEVICE_ID 0x{:08X}".format(device_id)) - return device_id - - def get_proto_ver(self): - """ - Return RFNoC protocol version - """ - with self.regs: - reg_val = self.peek32(self.MB_RFNOC_INFO) - proto_ver = (reg_val & 0x0000ffff) >> self.MB_RFNOC_INFO_PROTO_VER - self.log.trace("Read RFNOC_PROTO_VER 0x{:08X}".format(proto_ver)) - return proto_ver; - - def get_chdr_width(self): - """ - Return RFNoC CHDR width - """ - with self.regs: - reg_val = self.peek32(self.MB_RFNOC_INFO) - chdr_width = (reg_val & 0xffff0000) >> self.MB_RFNOC_INFO_CHDR_WIDTH - self.log.trace("Read RFNOC_CHDR_WIDTH 0x{:08X}".format(chdr_width)) - return chdr_width + MboardRegsCommon.__init__(self, label, log) def set_fp_gpio_master(self, value): """set driver for front panel GPIO @@ -308,43 +231,6 @@ class MboardRegsControl(object): with self.regs: return self.peek32(self.MB_GPIO_RADIO_SRC) & 0xffffff - def get_build_timestamp(self): - """ - Returns the build date/time for the FPGA image. - The return is datetime string with the ISO 8601 format - (YYYY-MM-DD HH:MM:SS.mmmmmm) - """ - with self.regs: - datestamp_rb = self.peek32(self.MB_DATESTAMP) - if datestamp_rb > 0: - dt_str = datetime.datetime( - year=((datestamp_rb>>17)&0x3F)+2000, - month=(datestamp_rb>>23)&0x0F, - day=(datestamp_rb>>27)&0x1F, - hour=(datestamp_rb>>12)&0x1F, - minute=(datestamp_rb>>6)&0x3F, - second=((datestamp_rb>>0)&0x3F)) - self.log.trace("FPGA build timestamp: {}".format(str(dt_str))) - return str(dt_str) - else: - # Compatibility with FPGAs without datestamp capability - return '' - - def get_git_hash(self): - """ - Returns the GIT hash for the FPGA build. - The return is a tuple of - 2 numbers: (short git hash, bool: is the tree dirty?) - """ - with self.regs: - git_hash_rb = self.peek32(self.MB_GIT_HASH) - git_hash = git_hash_rb & 0x0FFFFFFF - tree_dirty = ((git_hash_rb & 0xF0000000) > 0) - dirtiness_qualifier = 'dirty' if tree_dirty else 'clean' - self.log.trace("FPGA build GIT Hash: {:07x} ({})".format( - git_hash, dirtiness_qualifier)) - return (git_hash, dirtiness_qualifier) - def set_time_source(self, time_source, ref_clk_freq): """ Set time source |