aboutsummaryrefslogtreecommitdiffstats
path: root/mpm/python/usrp_mpm/periph_manager/e320.py
diff options
context:
space:
mode:
Diffstat (limited to 'mpm/python/usrp_mpm/periph_manager/e320.py')
-rw-r--r--mpm/python/usrp_mpm/periph_manager/e320.py19
1 files changed, 19 insertions, 0 deletions
diff --git a/mpm/python/usrp_mpm/periph_manager/e320.py b/mpm/python/usrp_mpm/periph_manager/e320.py
index f3a8da12d..c06ba897a 100644
--- a/mpm/python/usrp_mpm/periph_manager/e320.py
+++ b/mpm/python/usrp_mpm/periph_manager/e320.py
@@ -463,6 +463,25 @@ class e320(ZynqComponents, PeriphManagerBase):
self._time_source = time_source
self.mboard_regs_control.set_time_source(time_source, self.get_ref_clock_freq())
+ def get_sync_sources(self):
+ """
+ List sync sources.
+ """
+ valid_sync_sources = {
+ # clock, time. Reminder: 'internal' is an alias for 'gpsdo'
+ # pylint: disable=bad-whitespace
+ ('internal', 'internal'),
+ ('external', 'internal'),
+ ('external', 'external'),
+ ('gpsdo', 'gpsdo' ),
+ ('gpsdo', 'internal'),
+ # pylint: enable=bad-whitespace
+ }
+ return [{
+ "time_source": time_source,
+ "clock_source": clock_source
+ } for (clock_source, time_source) in valid_sync_sources]
+
###########################################################################
# GPIO API
###########################################################################