diff options
Diffstat (limited to 'mpm/python/usrp_mpm/dboard_manager')
| -rw-r--r-- | mpm/python/usrp_mpm/dboard_manager/magnesium.py | 3 | ||||
| -rw-r--r-- | mpm/python/usrp_mpm/dboard_manager/mg_init.py | 7 |
2 files changed, 8 insertions, 2 deletions
diff --git a/mpm/python/usrp_mpm/dboard_manager/magnesium.py b/mpm/python/usrp_mpm/dboard_manager/magnesium.py index 06dff175f..ca3c74e4b 100644 --- a/mpm/python/usrp_mpm/dboard_manager/magnesium.py +++ b/mpm/python/usrp_mpm/dboard_manager/magnesium.py @@ -422,7 +422,8 @@ class Magnesium(DboardManagerBase): db_clk_control = DboardClockControl(dboard_ctrl_regs, self.log) db_clk_control.reset_mmcm() # Place the JESD204b core in reset, mainly to reset QPLL/CPLLs. - jesdcore = nijesdcore.NIMgJESDCore(dboard_ctrl_regs, self.slot_idx) + jesdcore = nijesdcore.NIJESDCore(dboard_ctrl_regs, self.slot_idx, + **MagnesiumInitManager.JESD_DEFAULT_ARGS) jesdcore.reset() # The reference clock is handled elsewhere since it is a motherboard- # level clock. diff --git a/mpm/python/usrp_mpm/dboard_manager/mg_init.py b/mpm/python/usrp_mpm/dboard_manager/mg_init.py index 62cc27a4f..d2b597c21 100644 --- a/mpm/python/usrp_mpm/dboard_manager/mg_init.py +++ b/mpm/python/usrp_mpm/dboard_manager/mg_init.py @@ -76,6 +76,11 @@ class MagnesiumInitManager(object): # Variable PPS delay before the RP/SP pulsers begin. Fixed value for the # N3xx devices. N3XX_INT_PPS_DELAY = 4 + # JESD core default configuration. + JESD_DEFAULT_ARGS = {"bypass_descrambler": False, + "lmfc_divider" : 20, + "rx_sysref_delay" : 8, + "tx_sysref_delay" : 11} def __init__(self, mg_class, spi_ifaces): self.mg_class = mg_class @@ -525,7 +530,7 @@ class MagnesiumInitManager(object): read_only=False ) as dboard_ctrl_regs: self.log.trace("Creating jesdcore object...") - jesdcore = nijesdcore.NIMgJESDCore(dboard_ctrl_regs, slot_idx) + jesdcore = nijesdcore.NIJESDCore(dboard_ctrl_regs, slot_idx, **self.JESD_DEFAULT_ARGS) # Now get cracking with the actual init sequence: self.log.trace("Creating dboard clock control object...") db_clk_control = DboardClockControl(dboard_ctrl_regs, self.log) |