diff options
Diffstat (limited to 'mpm/python/usrp_mpm/dboard_manager')
| -rw-r--r-- | mpm/python/usrp_mpm/dboard_manager/base.py | 6 | ||||
| -rw-r--r-- | mpm/python/usrp_mpm/dboard_manager/eiscat.py | 37 | ||||
| -rw-r--r-- | mpm/python/usrp_mpm/dboard_manager/lmk_eiscat.py | 7 | ||||
| -rw-r--r-- | mpm/python/usrp_mpm/dboard_manager/magnesium.py | 2 |
4 files changed, 43 insertions, 9 deletions
diff --git a/mpm/python/usrp_mpm/dboard_manager/base.py b/mpm/python/usrp_mpm/dboard_manager/base.py index 52d2f22a3..13284f6d3 100644 --- a/mpm/python/usrp_mpm/dboard_manager/base.py +++ b/mpm/python/usrp_mpm/dboard_manager/base.py @@ -34,3 +34,9 @@ class DboardManagerBase(object): def get_serial(self): return self._eeprom.get("serial", "") + + def update_ref_clock_freq(self, freq): + """ + Call this function if the frequency of the reference clock changes. + """ + self.log.warning("update_ref_clock_freq() called but not implemented") diff --git a/mpm/python/usrp_mpm/dboard_manager/eiscat.py b/mpm/python/usrp_mpm/dboard_manager/eiscat.py index da8b1eb05..552072fe9 100644 --- a/mpm/python/usrp_mpm/dboard_manager/eiscat.py +++ b/mpm/python/usrp_mpm/dboard_manager/eiscat.py @@ -197,10 +197,10 @@ class JesdCoreEiscat(object): ADDR_BASE = 0x0000 ADDR_OFFSET = 0x1000 - def __init__(self, regs, slot, core_idx, log): + def __init__(self, regs, slot_idx, core_idx, log): self.log = log self.regs = regs - self.slot = slot + self.slot = "A" if slot_idx == 0 else "B" assert core_idx in (0, 1) self.core_idx = core_idx self.base_addr = self.ADDR_BASE + self.ADDR_OFFSET * self.core_idx @@ -346,10 +346,13 @@ class EISCAT(DboardManagerBase): "adc1": 2 } - def __init__(self, spi_devices, *args, **kwargs): + def __init__(self, slot_idx, spi_devices, *args, **kwargs): super(EISCAT, self).__init__(*args, **kwargs) self.log = get_logger("EISCAT") - self.log.trace("Initializing EISCAT daughterbaord") + self.slot_idx = slot_idx + self.log.trace("Initializing EISCAT daughterboard, slot index {}".format(self.slot_idx)) + self.initialized = False + self.ref_clock_freq = 10e6 if len(spi_devices) < len(self.spi_chipselect): self.log.error("Expected {0} spi devices, found {1} spi devices".format( len(self.spi_chipselect), len(spi_devices), @@ -369,6 +372,7 @@ class EISCAT(DboardManagerBase): self.lmk = None self.adc0 = None self.adc1 = None + self.mmcm = None def init_device(self): """ @@ -387,7 +391,7 @@ class EISCAT(DboardManagerBase): self.jesd_cores = [ JesdCoreEiscat( self.radio_regs, - "A", # TODO fix hard-coded slot number + self.slot_idx, core_idx, self.log ) for core_idx in xrange(2) @@ -400,7 +404,7 @@ class EISCAT(DboardManagerBase): self.mmcm = MMCM(self.radio_regs, self.log) self._init_power(self.radio_regs) self.mmcm.reset() - self.lmk = LMK04828EISCAT(self._spi_ifaces['lmk'], "A") # Initializes LMK + self.lmk = LMK04828EISCAT(self._spi_ifaces['lmk'], self.ref_clock_freq, "A") # Initializes LMK if not self.mmcm.enable(): self.log.error("Could not re-enable MMCM!") raise RuntimeError("Could not re-enable MMCM!") @@ -442,6 +446,14 @@ class EISCAT(DboardManagerBase): if not self.jesd_cores[i].check_deframer_status(): raise RuntimeError("JESD Core {}: Deframer status not lookin' so good!".format(i)) ## END OF THE JEPSON SEQUENCE ## + self.initialized = True + + def shutdown(self): + """ + Safely turn off the daughterboard + """ + self.log.info("Shutting down daughterboard") + self._deinit_power() def _init_power(self, regs): @@ -475,3 +487,16 @@ class EISCAT(DboardManagerBase): self.log.trace("Disabling power to the daughterboard...") regs.poke32(POWER_ENB, 0x0000) + def update_ref_clock_freq(self, freq): + """ + Call this to notify the daughterboard about a change in reference clock + """ + self.ref_clock_freq = freq + if self.initialized: + self.log.warning( + "Attempting to update external reference clock frequency " + "after initialization! This will only take effect after " + "the daughterboard is re-initialized." + ) + + diff --git a/mpm/python/usrp_mpm/dboard_manager/lmk_eiscat.py b/mpm/python/usrp_mpm/dboard_manager/lmk_eiscat.py index f5114607a..f169e2589 100644 --- a/mpm/python/usrp_mpm/dboard_manager/lmk_eiscat.py +++ b/mpm/python/usrp_mpm/dboard_manager/lmk_eiscat.py @@ -27,9 +27,11 @@ class LMK04828EISCAT(object): """ LMK04828 controls for EISCAT daughterboard """ - def __init__(self, regs_iface, slot=None): + def __init__(self, regs_iface, ref_clock_freq, slot=None): slot = slot or "-A" self.log = get_logger("LMK04828"+slot) + assert ref_clock_freq in (10e6, 20e6) + self.ref_clock_freq = ref_clock_freq self.regs_iface = regs_iface self.init() self.config() @@ -61,6 +63,7 @@ class LMK04828EISCAT(object): Write lots of config foo. """ self.log.trace("Setting clkout config...") + CLKin0_R_divider = {10e6: 0x0A, 20e6: 0x14}[self.ref_clock_freq] self.pokes8(( (0x100, 0x6C), # CLKout Config (0x101, 0x55), # CLKout Config @@ -139,7 +142,7 @@ class LMK04828EISCAT(object): (0x151, 0x02), # Holdover Settings (defaults) (0x152, 0x00), # Holdover Settings (defaults) (0x153, 0x00), # CLKin0_R divider [13:8], default = 0 - (0x154, 0x0A), # CLKin0_R divider [7:0], default = d120 + (0x154, CLKin0_R_divider), # CLKin0_R divider [7:0], default = d120 (0x155, 0x00), # CLKin1_R divider [13:8], default = 0 (0x156, 0x01), # CLKin1_R divider [7:0], default = d120 (0x157, 0x00), # CLKin2_R divider [13:8], default = 0 diff --git a/mpm/python/usrp_mpm/dboard_manager/magnesium.py b/mpm/python/usrp_mpm/dboard_manager/magnesium.py index aa667e1e0..fa2dbe9c3 100644 --- a/mpm/python/usrp_mpm/dboard_manager/magnesium.py +++ b/mpm/python/usrp_mpm/dboard_manager/magnesium.py @@ -36,7 +36,7 @@ class Magnesium(DboardManagerBase): # Maps the chipselects to the corresponding devices: spi_chipselect = {"lmk": 0, "mykonos": 1} - def __init__(self, spi_devices, eeprom_data, *args, **kwargs): + def __init__(self, slot_idx, spi_devices, eeprom_data, *args, **kwargs): super(Magnesium, self).__init__(*args, **kwargs) self.log = get_logger("Magnesium") # eeprom_data is a tuple (head_dict, raw_data) |