diff options
Diffstat (limited to 'host')
| -rw-r--r-- | host/lib/usrp/usrp2/CMakeLists.txt | 1 | ||||
| -rw-r--r-- | host/lib/usrp/usrp2/codec_ctrl.cpp | 4 | ||||
| -rw-r--r-- | host/lib/usrp/usrp2/dboard_iface.cpp | 30 | ||||
| -rw-r--r-- | host/lib/usrp/usrp2/dsp_impl.cpp | 40 | ||||
| -rw-r--r-- | host/lib/usrp/usrp2/mboard_impl.cpp | 58 | ||||
| -rw-r--r-- | host/lib/usrp/usrp2/usrp2_iface.cpp | 5 | ||||
| -rw-r--r-- | host/lib/usrp/usrp2/usrp2_iface.hpp | 5 | ||||
| -rw-r--r-- | host/lib/usrp/usrp2/usrp2_regs.cpp | 136 | ||||
| -rw-r--r-- | host/lib/usrp/usrp2/usrp2_regs.hpp | 284 |
9 files changed, 174 insertions, 389 deletions
diff --git a/host/lib/usrp/usrp2/CMakeLists.txt b/host/lib/usrp/usrp2/CMakeLists.txt index 49be9ac7d..c3f138c24 100644 --- a/host/lib/usrp/usrp2/CMakeLists.txt +++ b/host/lib/usrp/usrp2/CMakeLists.txt @@ -41,6 +41,5 @@ IF(ENABLE_USRP2) ${CMAKE_CURRENT_SOURCE_DIR}/usrp2_impl.cpp ${CMAKE_CURRENT_SOURCE_DIR}/usrp2_impl.hpp ${CMAKE_CURRENT_SOURCE_DIR}/usrp2_regs.hpp - ${CMAKE_CURRENT_SOURCE_DIR}/usrp2_regs.cpp ) ENDIF(ENABLE_USRP2) diff --git a/host/lib/usrp/usrp2/codec_ctrl.cpp b/host/lib/usrp/usrp2/codec_ctrl.cpp index 796888b8f..b32a9f256 100644 --- a/host/lib/usrp/usrp2/codec_ctrl.cpp +++ b/host/lib/usrp/usrp2/codec_ctrl.cpp @@ -61,7 +61,7 @@ public: switch(_iface->get_rev()){ case usrp2_iface::USRP2_REV3: case usrp2_iface::USRP2_REV4: - _iface->poke32(_iface->regs.misc_ctrl_adc, U2_FLAG_MISC_CTRL_ADC_ON); + _iface->poke32(U2_REG_MISC_CTRL_ADC, U2_FLAG_MISC_CTRL_ADC_ON); break; case usrp2_iface::USRP_N200: @@ -88,7 +88,7 @@ public: switch(_iface->get_rev()){ case usrp2_iface::USRP2_REV3: case usrp2_iface::USRP2_REV4: - _iface->poke32(_iface->regs.misc_ctrl_adc, U2_FLAG_MISC_CTRL_ADC_OFF); + _iface->poke32(U2_REG_MISC_CTRL_ADC, U2_FLAG_MISC_CTRL_ADC_OFF); break; case usrp2_iface::USRP_N200: diff --git a/host/lib/usrp/usrp2/dboard_iface.cpp b/host/lib/usrp/usrp2/dboard_iface.cpp index 924a6e901..4ce49b409 100644 --- a/host/lib/usrp/usrp2/dboard_iface.cpp +++ b/host/lib/usrp/usrp2/dboard_iface.cpp @@ -180,8 +180,8 @@ void usrp2_dboard_iface::_set_pin_ctrl(unit_t unit, boost::uint16_t value){ //write the selection mux value to register switch(unit){ - case UNIT_RX: _iface->poke32(_iface->regs.gpio_rx_sel, new_sels); return; - case UNIT_TX: _iface->poke32(_iface->regs.gpio_tx_sel, new_sels); return; + case UNIT_RX: _iface->poke32(U2_REG_GPIO_RX_SEL, new_sels); return; + case UNIT_TX: _iface->poke32(U2_REG_GPIO_TX_SEL, new_sels); return; } } @@ -189,18 +189,18 @@ void usrp2_dboard_iface::_set_gpio_ddr(unit_t unit, boost::uint16_t value){ _ddr_shadow = \ (_ddr_shadow & ~(0xffff << unit_to_shift[unit])) | (boost::uint32_t(value) << unit_to_shift[unit]); - _iface->poke32(_iface->regs.gpio_ddr, _ddr_shadow); + _iface->poke32(U2_REG_GPIO_DDR, _ddr_shadow); } void usrp2_dboard_iface::_set_gpio_out(unit_t unit, boost::uint16_t value){ _gpio_shadow = \ (_gpio_shadow & ~(0xffff << unit_to_shift[unit])) | (boost::uint32_t(value) << unit_to_shift[unit]); - _iface->poke32(_iface->regs.gpio_io, _gpio_shadow); + _iface->poke32(U2_REG_GPIO_IO, _gpio_shadow); } boost::uint16_t usrp2_dboard_iface::read_gpio(unit_t unit){ - return boost::uint16_t(_iface->peek32(_iface->regs.gpio_io) >> unit_to_shift[unit]); + return boost::uint16_t(_iface->peek32(U2_REG_GPIO_IO) >> unit_to_shift[unit]); } void usrp2_dboard_iface::_set_atr_reg(unit_t unit, atr_reg_t atr, boost::uint16_t value){ @@ -209,16 +209,16 @@ void usrp2_dboard_iface::_set_atr_reg(unit_t unit, atr_reg_t atr, boost::uint16_ unit_t, uhd::dict<atr_reg_t, boost::uint32_t> > unit_to_atr_to_addr = map_list_of (UNIT_RX, map_list_of - (ATR_REG_IDLE, _iface->regs.atr_idle_rxside) - (ATR_REG_TX_ONLY, _iface->regs.atr_intx_rxside) - (ATR_REG_RX_ONLY, _iface->regs.atr_inrx_rxside) - (ATR_REG_FULL_DUPLEX, _iface->regs.atr_full_rxside) + (ATR_REG_IDLE, U2_REG_ATR_IDLE_RXSIDE) + (ATR_REG_TX_ONLY, U2_REG_ATR_INTX_RXSIDE) + (ATR_REG_RX_ONLY, U2_REG_ATR_INRX_RXSIDE) + (ATR_REG_FULL_DUPLEX, U2_REG_ATR_FULL_RXSIDE) ) (UNIT_TX, map_list_of - (ATR_REG_IDLE, _iface->regs.atr_idle_txside) - (ATR_REG_TX_ONLY, _iface->regs.atr_intx_txside) - (ATR_REG_RX_ONLY, _iface->regs.atr_inrx_txside) - (ATR_REG_FULL_DUPLEX, _iface->regs.atr_full_txside) + (ATR_REG_IDLE, U2_REG_ATR_IDLE_TXSIDE) + (ATR_REG_TX_ONLY, U2_REG_ATR_INTX_TXSIDE) + (ATR_REG_RX_ONLY, U2_REG_ATR_INRX_TXSIDE) + (ATR_REG_FULL_DUPLEX, U2_REG_ATR_FULL_TXSIDE) ) ; _iface->poke16(unit_to_atr_to_addr[unit][atr], value); @@ -238,8 +238,8 @@ void usrp2_dboard_iface::set_gpio_debug(unit_t unit, int which){ //write the selection mux value to register switch(unit){ - case UNIT_RX: _iface->poke32(_iface->regs.gpio_rx_sel, new_sels); return; - case UNIT_TX: _iface->poke32(_iface->regs.gpio_tx_sel, new_sels); return; + case UNIT_RX: _iface->poke32(U2_REG_GPIO_RX_SEL, new_sels); return; + case UNIT_TX: _iface->poke32(U2_REG_GPIO_TX_SEL, new_sels); return; } } diff --git a/host/lib/usrp/usrp2/dsp_impl.cpp b/host/lib/usrp/usrp2/dsp_impl.cpp index cdd559e94..292659f36 100644 --- a/host/lib/usrp/usrp2/dsp_impl.cpp +++ b/host/lib/usrp/usrp2/dsp_impl.cpp @@ -68,18 +68,18 @@ void usrp2_mboard_impl::dsp_init(void){ ddc_set(DSP_PROP_HOST_RATE, double(get_master_clock_freq()/16), i); //setup the rx control registers - _iface->poke32(_iface->regs.rx_ctrl[i].clear_overrun, 1); //reset - _iface->poke32(_iface->regs.rx_ctrl[i].nsamps_per_pkt, _device.get_max_recv_samps_per_packet()); - _iface->poke32(_iface->regs.rx_ctrl[i].nchannels, 1); - _iface->poke32(_iface->regs.rx_ctrl[i].vrt_header, 0 + _iface->poke32(U2_REG_RX_CTRL_CLEAR(i), 1); //reset + _iface->poke32(U2_REG_RX_CTRL_NSAMPS_PP(i), _device.get_max_recv_samps_per_packet()); + _iface->poke32(U2_REG_RX_CTRL_NCHANNELS(i), 1); + _iface->poke32(U2_REG_RX_CTRL_VRT_HDR(i), 0 | (0x1 << 28) //if data with stream id | (0x1 << 26) //has trailer | (0x3 << 22) //integer time other | (0x1 << 20) //fractional time sample count ); - _iface->poke32(_iface->regs.rx_ctrl[i].vrt_stream_id, usrp2_impl::RECV_SID); - _iface->poke32(_iface->regs.rx_ctrl[i].vrt_trailer, 0); - _iface->poke32(_iface->regs.time64_tps, size_t(get_master_clock_freq())); + _iface->poke32(U2_REG_RX_CTRL_VRT_SID(i), usrp2_impl::RECV_SID); + _iface->poke32(U2_REG_RX_CTRL_VRT_TLR(i), 0); + _iface->poke32(U2_REG_TIME64_TPS, size_t(get_master_clock_freq())); } //bind and initialize the tx dsps @@ -94,10 +94,10 @@ void usrp2_mboard_impl::dsp_init(void){ duc_set(DSP_PROP_HOST_RATE, double(get_master_clock_freq()/16), i); //init the tx control registers - _iface->poke32(_iface->regs.tx_ctrl_clear_state, 1); //reset - _iface->poke32(_iface->regs.tx_ctrl_num_chan, 0); //1 channel - _iface->poke32(_iface->regs.tx_ctrl_report_sid, usrp2_impl::ASYNC_SID); - _iface->poke32(_iface->regs.tx_ctrl_policy, U2_FLAG_TX_CTRL_POLICY_NEXT_PACKET); + _iface->poke32(U2_REG_TX_CTRL_CLEAR_STATE, 1); //reset + _iface->poke32(U2_REG_TX_CTRL_NUM_CHAN, 0); //1 channel + _iface->poke32(U2_REG_TX_CTRL_REPORT_SID, usrp2_impl::ASYNC_SID); + _iface->poke32(U2_REG_TX_CTRL_POLICY, U2_FLAG_TX_CTRL_POLICY_NEXT_PACKET); } } @@ -113,9 +113,9 @@ static rate_type pick_closest_rate(double exact_rate, const std::vector<rate_typ void usrp2_mboard_impl::issue_ddc_stream_cmd(const stream_cmd_t &stream_cmd, size_t which_dsp){ _dsp_impl->continuous_streaming[which_dsp] = stream_cmd.stream_mode == stream_cmd_t::STREAM_MODE_START_CONTINUOUS; - _iface->poke32(_iface->regs.rx_ctrl[which_dsp].stream_cmd, dsp_type1::calc_stream_cmd_word(stream_cmd)); - _iface->poke32(_iface->regs.rx_ctrl[which_dsp].time_secs, boost::uint32_t(stream_cmd.time_spec.get_full_secs())); - _iface->poke32(_iface->regs.rx_ctrl[which_dsp].time_ticks, stream_cmd.time_spec.get_tick_count(get_master_clock_freq())); + _iface->poke32(U2_REG_RX_CTRL_STREAM_CMD(which_dsp), dsp_type1::calc_stream_cmd_word(stream_cmd)); + _iface->poke32(U2_REG_RX_CTRL_TIME_SECS(which_dsp), boost::uint32_t(stream_cmd.time_spec.get_full_secs())); + _iface->poke32(U2_REG_RX_CTRL_TIME_TICKS(which_dsp), stream_cmd.time_spec.get_tick_count(get_master_clock_freq())); } void usrp2_mboard_impl::handle_overflow(size_t which_dsp){ @@ -166,7 +166,7 @@ void usrp2_mboard_impl::ddc_set(const wax::obj &key_, const wax::obj &val, size_ case DSP_PROP_FREQ_SHIFT:{ double new_freq = val.as<double>(); - _iface->poke32(_iface->regs.dsp_rx[which_dsp].freq, + _iface->poke32(U2_REG_DSP_RX_FREQ(which_dsp), dsp_type1::calc_cordic_word_and_update(new_freq, get_master_clock_freq()) ); _dsp_impl->ddc_freq[which_dsp] = new_freq; //shadow @@ -178,11 +178,11 @@ void usrp2_mboard_impl::ddc_set(const wax::obj &key_, const wax::obj &val, size_ _dsp_impl->ddc_decim[which_dsp] = pick_closest_rate(extact_rate, _dsp_impl->decim_and_interp_rates); //set the decimation - _iface->poke32(_iface->regs.dsp_rx[which_dsp].decim_rate, dsp_type1::calc_cic_filter_word(_dsp_impl->ddc_decim[which_dsp])); + _iface->poke32(U2_REG_DSP_RX_DECIM(which_dsp), dsp_type1::calc_cic_filter_word(_dsp_impl->ddc_decim[which_dsp])); //set the scaling static const boost::int16_t default_rx_scale_iq = 1024; - _iface->poke32(_iface->regs.dsp_rx[which_dsp].scale_iq, + _iface->poke32(U2_REG_DSP_RX_SCALE_IQ(which_dsp), dsp_type1::calc_iq_scale_word(default_rx_scale_iq, default_rx_scale_iq) ); } @@ -242,7 +242,7 @@ void usrp2_mboard_impl::duc_set(const wax::obj &key_, const wax::obj &val, size_ if (zone == 0) _codec_ctrl->set_tx_mod_mode(0); //no shift else _codec_ctrl->set_tx_mod_mode(sign*4/zone); //DAC interp = 4 - _iface->poke32(_iface->regs.dsp_tx_freq, + _iface->poke32(U2_REG_DSP_TX_FREQ, dsp_type1::calc_cordic_word_and_update(new_freq, codec_rate) ); _dsp_impl->duc_freq[which_dsp] = new_freq + dac_shift; //shadow @@ -254,10 +254,10 @@ void usrp2_mboard_impl::duc_set(const wax::obj &key_, const wax::obj &val, size_ _dsp_impl->duc_interp[which_dsp] = pick_closest_rate(extact_rate, _dsp_impl->decim_and_interp_rates); //set the interpolation - _iface->poke32(_iface->regs.dsp_tx_interp_rate, dsp_type1::calc_cic_filter_word(_dsp_impl->duc_interp[which_dsp])); + _iface->poke32(U2_REG_DSP_TX_INTERP_RATE, dsp_type1::calc_cic_filter_word(_dsp_impl->duc_interp[which_dsp])); //set the scaling - _iface->poke32(_iface->regs.dsp_tx_scale_iq, dsp_type1::calc_iq_scale_word(_dsp_impl->duc_interp[which_dsp])); + _iface->poke32(U2_REG_DSP_TX_SCALE_IQ, dsp_type1::calc_iq_scale_word(_dsp_impl->duc_interp[which_dsp])); } return; diff --git a/host/lib/usrp/usrp2/mboard_impl.cpp b/host/lib/usrp/usrp2/mboard_impl.cpp index bb4d90dd6..2885e57e4 100644 --- a/host/lib/usrp/usrp2/mboard_impl.cpp +++ b/host/lib/usrp/usrp2/mboard_impl.cpp @@ -71,7 +71,7 @@ usrp2_mboard_impl::usrp2_mboard_impl( { //check the fpga compatibility number - const boost::uint32_t fpga_compat_num = _iface->peek32(_iface->regs.compat_num_rb); + const boost::uint32_t fpga_compat_num = _iface->peek32(U2_REG_COMPAT_NUM_RB); if (fpga_compat_num != USRP2_FPGA_COMPAT_NUM){ throw uhd::runtime_error(str(boost::format( "\nPlease update the firmware and FPGA images for your device.\n" @@ -119,7 +119,7 @@ usrp2_mboard_impl::usrp2_mboard_impl( const double ups_per_sec = device_addr.cast<double>("ups_per_sec", 0.0); if (ups_per_sec > 0.0){ const size_t cycles_per_up = size_t(_clock_ctrl->get_master_clock_rate()/ups_per_sec); - _iface->poke32(_iface->regs.tx_ctrl_cycles_per_up, U2_FLAG_TX_CTRL_UP_ENB | cycles_per_up); + _iface->poke32(U2_REG_TX_CTRL_CYCLES_PER_UP, U2_FLAG_TX_CTRL_UP_ENB | cycles_per_up); } //setting the packets per update (enabled by default) @@ -127,7 +127,7 @@ usrp2_mboard_impl::usrp2_mboard_impl( const double ups_per_fifo = device_addr.cast<double>("ups_per_fifo", 8.0); if (ups_per_fifo > 0.0){ const size_t packets_per_up = size_t(usrp2_impl::sram_bytes/ups_per_fifo/send_frame_size); - _iface->poke32(_iface->regs.tx_ctrl_packets_per_up, U2_FLAG_TX_CTRL_UP_ENB | packets_per_up); + _iface->poke32(U2_REG_TX_CTRL_PACKETS_PER_UP, U2_FLAG_TX_CTRL_UP_ENB | packets_per_up); } //initialize the clock configuration @@ -143,7 +143,7 @@ usrp2_mboard_impl::usrp2_mboard_impl( ); } else { - _mimo_clocking_mode_is_master = (_iface->peek32(_iface->regs.status) & (1 << 8)) != 0; + _mimo_clocking_mode_is_master = (_iface->peek32(U2_REG_STATUS) & (1 << 8)) != 0; } UHD_MSG(status) << boost::format("mboard%d is MIMO %s") % _index % (_mimo_clocking_mode_is_master?"master":"slave") << std::endl; @@ -171,7 +171,7 @@ usrp2_mboard_impl::usrp2_mboard_impl( this->issue_ddc_stream_cmd(stream_cmd, i); device.dsp_xports.at(index)->get_recv_buff(0.01).get(); //recv with timeout for lingering device.dsp_xports.at(index)->get_recv_buff(0.01).get(); //recv with timeout for expected - _iface->poke32(_iface->regs.rx_ctrl[i].clear_overrun, 1); //resets sequence + _iface->poke32(U2_REG_RX_CTRL_CLEAR(i), 1); //resets sequence } //------------------------------------------------------------------ } @@ -180,8 +180,8 @@ usrp2_mboard_impl::~usrp2_mboard_impl(void){ //Safely destruct all RAII objects in an mboard. //This prevents the mboard deconstructor from throwing, //which allows the device to be safely deconstructed. - UHD_SAFE_CALL(_iface->poke32(_iface->regs.tx_ctrl_cycles_per_up, 0);) - UHD_SAFE_CALL(_iface->poke32(_iface->regs.tx_ctrl_packets_per_up, 0);) + UHD_SAFE_CALL(_iface->poke32(U2_REG_TX_CTRL_CYCLES_PER_UP, 0);) + UHD_SAFE_CALL(_iface->poke32(U2_REG_TX_CTRL_PACKETS_PER_UP, 0);) UHD_SAFE_CALL(_dboard_manager.reset();) UHD_SAFE_CALL(_dboard_iface.reset();) UHD_SAFE_CALL(_codec_ctrl.reset();) @@ -204,13 +204,13 @@ void usrp2_mboard_impl::update_clock_config(void){ //translate pps source enums switch(_clock_config.pps_source){ case clock_config_t::PPS_MIMO: - _iface->poke32(_iface->regs.time64_mimo_sync, + _iface->poke32(U2_REG_TIME64_MIMO_SYNC, (1 << 8) | (mimo_clock_sync_delay_cycles & 0xff) ); break; case clock_config_t::PPS_SMA: - _iface->poke32(_iface->regs.time64_mimo_sync, 0); + _iface->poke32(U2_REG_TIME64_MIMO_SYNC, 0); pps_flags |= U2_FLAG_TIME64_PPS_SMA; break; @@ -225,16 +225,16 @@ void usrp2_mboard_impl::update_clock_config(void){ } //set the pps flags - _iface->poke32(_iface->regs.time64_flags, pps_flags); + _iface->poke32(U2_REG_TIME64_FLAGS, pps_flags); //clock source ref 10mhz switch(_iface->get_rev()){ case usrp2_iface::USRP_N200: case usrp2_iface::USRP_N210: switch(_clock_config.ref_source){ - case clock_config_t::REF_INT : _iface->poke32(_iface->regs.misc_ctrl_clock, 0x12); break; - case clock_config_t::REF_SMA : _iface->poke32(_iface->regs.misc_ctrl_clock, 0x1C); break; - case clock_config_t::REF_MIMO: _iface->poke32(_iface->regs.misc_ctrl_clock, 0x15); break; + case clock_config_t::REF_INT : _iface->poke32(U2_REG_MISC_CTRL_CLOCK, 0x12); break; + case clock_config_t::REF_SMA : _iface->poke32(U2_REG_MISC_CTRL_CLOCK, 0x1C); break; + case clock_config_t::REF_MIMO: _iface->poke32(U2_REG_MISC_CTRL_CLOCK, 0x15); break; default: throw uhd::value_error("unhandled clock configuration reference source"); } _clock_ctrl->enable_external_ref(true); //USRP2P has an internal 10MHz TCXO @@ -243,9 +243,9 @@ void usrp2_mboard_impl::update_clock_config(void){ case usrp2_iface::USRP2_REV3: case usrp2_iface::USRP2_REV4: switch(_clock_config.ref_source){ - case clock_config_t::REF_INT : _iface->poke32(_iface->regs.misc_ctrl_clock, 0x10); break; - case clock_config_t::REF_SMA : _iface->poke32(_iface->regs.misc_ctrl_clock, 0x1C); break; - case clock_config_t::REF_MIMO: _iface->poke32(_iface->regs.misc_ctrl_clock, 0x15); break; + case clock_config_t::REF_INT : _iface->poke32(U2_REG_MISC_CTRL_CLOCK, 0x10); break; + case clock_config_t::REF_SMA : _iface->poke32(U2_REG_MISC_CTRL_CLOCK, 0x1C); break; + case clock_config_t::REF_MIMO: _iface->poke32(U2_REG_MISC_CTRL_CLOCK, 0x15); break; default: throw uhd::value_error("unhandled clock configuration reference source"); } _clock_ctrl->enable_external_ref(_clock_config.ref_source != clock_config_t::REF_INT); @@ -280,14 +280,14 @@ void usrp2_mboard_impl::set_time_spec(const time_spec_t &time_spec, bool now){ if (not _mimo_clocking_mode_is_master) return; //set the ticks - _iface->poke32(_iface->regs.time64_ticks, time_spec.get_tick_count(get_master_clock_freq())); + _iface->poke32(U2_REG_TIME64_TICKS, time_spec.get_tick_count(get_master_clock_freq())); //set the flags register boost::uint32_t imm_flags = (now)? U2_FLAG_TIME64_LATCH_NOW : U2_FLAG_TIME64_LATCH_NEXT_PPS; - _iface->poke32(_iface->regs.time64_imm, imm_flags); + _iface->poke32(U2_REG_TIME64_IMM, imm_flags); //set the seconds (latches in all 3 registers) - _iface->poke32(_iface->regs.time64_secs, boost::uint32_t(time_spec.get_full_secs())); + _iface->poke32(U2_REG_TIME64_SECS, boost::uint32_t(time_spec.get_full_secs())); } /*********************************************************************** @@ -346,17 +346,17 @@ void usrp2_mboard_impl::get(const wax::obj &key_, wax::obj &val){ return; case MBOARD_PROP_TIME_NOW: while(true){ - uint32_t secs = _iface->peek32(_iface->regs.time64_secs_rb_imm); - uint32_t ticks = _iface->peek32(_iface->regs.time64_ticks_rb_imm); - if (secs != _iface->peek32(_iface->regs.time64_secs_rb_imm)) continue; + uint32_t secs = _iface->peek32(U2_REG_TIME64_SECS_RB_IMM); + uint32_t ticks = _iface->peek32(U2_REG_TIME64_TICKS_RB_IMM); + if (secs != _iface->peek32(U2_REG_TIME64_SECS_RB_IMM)) continue; val = time_spec_t(secs, ticks, get_master_clock_freq()); return; } case MBOARD_PROP_TIME_PPS: while(true){ - uint32_t secs = _iface->peek32(_iface->regs.time64_secs_rb_pps); - uint32_t ticks = _iface->peek32(_iface->regs.time64_ticks_rb_pps); - if (secs != _iface->peek32(_iface->regs.time64_secs_rb_pps)) continue; + uint32_t secs = _iface->peek32(U2_REG_TIME64_SECS_RB_PPS); + uint32_t ticks = _iface->peek32(U2_REG_TIME64_TICKS_RB_PPS); + if (secs != _iface->peek32(U2_REG_TIME64_SECS_RB_PPS)) continue; val = time_spec_t(secs, ticks, get_master_clock_freq()); return; } @@ -406,11 +406,11 @@ void usrp2_mboard_impl::get(const wax::obj &key_, wax::obj &val){ } bool usrp2_mboard_impl::get_mimo_locked(void) { - return bool((_iface->peek32(_iface->regs.irq_rb) & (1<<10)) > 0); + return bool((_iface->peek32(U2_REG_IRQ_RB) & (1<<10)) > 0); } bool usrp2_mboard_impl::get_ref_locked(void) { - return bool((_iface->peek32(_iface->regs.irq_rb) & (1<<11)) > 0); + return bool((_iface->peek32(U2_REG_IRQ_RB) & (1<<11)) > 0); } /*********************************************************************** @@ -440,7 +440,7 @@ void usrp2_mboard_impl::set(const wax::obj &key, const wax::obj &val){ UHD_ASSERT_THROW(_rx_subdev_spec.size() <= NUM_RX_DSPS); //set the mux for (size_t i = 0; i < _rx_subdev_spec.size(); i++){ - if (_rx_subdev_spec.size() >= 1) _iface->poke32(_iface->regs.dsp_rx[i].mux, dsp_type1::calc_rx_mux_word( + _iface->poke32(U2_REG_DSP_RX_MUX(i), dsp_type1::calc_rx_mux_word( _dboard_manager->get_rx_subdev(_rx_subdev_spec[i].sd_name)[SUBDEV_PROP_CONNECTION].as<subdev_conn_t>() )); } @@ -454,7 +454,7 @@ void usrp2_mboard_impl::set(const wax::obj &key, const wax::obj &val){ UHD_ASSERT_THROW(_tx_subdev_spec.size() <= NUM_TX_DSPS); //set the mux for (size_t i = 0; i < _rx_subdev_spec.size(); i++){ - _iface->poke32(_iface->regs.dsp_tx_mux, dsp_type1::calc_tx_mux_word( + _iface->poke32(U2_REG_DSP_TX_MUX, dsp_type1::calc_tx_mux_word( _dboard_manager->get_tx_subdev(_tx_subdev_spec[i].sd_name)[SUBDEV_PROP_CONNECTION].as<subdev_conn_t>() )); } diff --git a/host/lib/usrp/usrp2/usrp2_iface.cpp b/host/lib/usrp/usrp2/usrp2_iface.cpp index 2d80f145a..5e197d1f9 100644 --- a/host/lib/usrp/usrp2/usrp2_iface.cpp +++ b/host/lib/usrp/usrp2/usrp2_iface.cpp @@ -97,7 +97,6 @@ public: _protocol_compat = ntohl(ctrl_data.proto_ver); mb_eeprom = mboard_eeprom_t(*this, mboard_eeprom_t::MAP_N100); - regs = usrp2_get_regs(); //reg map identical across all boards } ~usrp2_iface_impl(void){ @@ -123,7 +122,7 @@ public: bool is_device_locked(void){ boost::uint32_t lock_secs = this->get_reg<boost::uint32_t, USRP2_REG_ACTION_FW_PEEK32>(U2_FW_REG_LOCK_TIME); boost::uint32_t lock_gpid = this->get_reg<boost::uint32_t, USRP2_REG_ACTION_FW_PEEK32>(U2_FW_REG_LOCK_GPID); - boost::uint32_t curr_secs = this->peek32(this->regs.time64_secs_rb_imm); + boost::uint32_t curr_secs = this->peek32(U2_REG_TIME64_SECS_RB_IMM); //if the difference is larger, assume not locked anymore if (curr_secs - lock_secs >= 3) return false; @@ -139,7 +138,7 @@ public: this->get_reg<boost::uint32_t, USRP2_REG_ACTION_FW_POKE32>(U2_FW_REG_LOCK_GPID, boost::uint32_t(get_gpid())); while(true){ //re-lock in loop - boost::uint32_t curr_secs = this->peek32(this->regs.time64_secs_rb_imm); + boost::uint32_t curr_secs = this->peek32(U2_REG_TIME64_SECS_RB_IMM); this->get_reg<boost::uint32_t, USRP2_REG_ACTION_FW_POKE32>(U2_FW_REG_LOCK_TIME, curr_secs); //sleep for a bit boost::this_thread::sleep(boost::posix_time::milliseconds(1500)); diff --git a/host/lib/usrp/usrp2/usrp2_iface.hpp b/host/lib/usrp/usrp2/usrp2_iface.hpp index e4d1a166b..f2b8a1e29 100644 --- a/host/lib/usrp/usrp2/usrp2_iface.hpp +++ b/host/lib/usrp/usrp2/usrp2_iface.hpp @@ -72,11 +72,6 @@ public: //! Is this device locked? virtual bool is_device_locked(void) = 0; - /*! - * Register map selected from USRP2/USRP2+. - */ - usrp2_regs_t regs; - //motherboard eeprom map structure uhd::usrp::mboard_eeprom_t mb_eeprom; }; diff --git a/host/lib/usrp/usrp2/usrp2_regs.cpp b/host/lib/usrp/usrp2/usrp2_regs.cpp deleted file mode 100644 index 240bc3bab..000000000 --- a/host/lib/usrp/usrp2/usrp2_regs.cpp +++ /dev/null @@ -1,136 +0,0 @@ -// -// Copyright 2010-2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see <http://www.gnu.org/licenses/>. -// - -#include "usrp2_regs.hpp" -#include "usrp2_iface.hpp" - -//////////////////////////////////////////////////////////////////////// -// Define slave bases -//////////////////////////////////////////////////////////////////////// -#define ROUTER_RAM_BASE 0x4000 -#define SPI_BASE 0x5000 -#define I2C_BASE 0x5400 -#define GPIO_BASE 0x5800 -#define READBACK_BASE 0x5C00 -#define ETH_BASE 0x6000 -#define SETTING_REGS_BASE 0x7000 -#define PIC_BASE 0x8000 -#define UART_BASE 0x8800 -#define ATR_BASE 0x8C00 - -//////////////////////////////////////////////////////////////////////// -// Setting register offsets -//////////////////////////////////////////////////////////////////////// -#define SR_MISC 0 // 7 regs -#define SR_SIMTIMER 8 // 2 -#define SR_TIME64 10 // 6 -#define SR_BUF_POOL 16 // 4 - -#define SR_RX_FRONT 24 // 5 -#define SR_RX_CTRL0 32 // 9 -#define SR_RX_DSP0 48 // 7 -#define SR_RX_CTRL1 80 // 9 -#define SR_RX_DSP1 96 // 7 - -#define SR_TX_FRONT 128 // ? -#define SR_TX_CTRL 144 // 6 -#define SR_TX_DSP 160 // 5 - -#define SR_UDP_SM 192 // 64 - -int sr_addr(int sr) { - return SETTING_REGS_BASE + (4 * sr); -} - -usrp2_regs_t usrp2_get_regs(void) { - usrp2_regs_t x; - x.misc_ctrl_clock = sr_addr(0); - x.misc_ctrl_serdes = sr_addr(1); - x.misc_ctrl_adc = sr_addr(2); - x.misc_ctrl_leds = sr_addr(3); - x.misc_ctrl_phy = sr_addr(4); - x.misc_ctrl_dbg_mux = sr_addr(5); - x.misc_ctrl_ram_page = sr_addr(6); - x.misc_ctrl_flush_icache = sr_addr(7); - x.misc_ctrl_led_src = sr_addr(8); - x.time64_secs = sr_addr(SR_TIME64 + 0); - x.time64_ticks = sr_addr(SR_TIME64 + 1); - x.time64_flags = sr_addr(SR_TIME64 + 2); - x.time64_imm = sr_addr(SR_TIME64 + 3); - x.time64_tps = sr_addr(SR_TIME64 + 4); - x.time64_mimo_sync = sr_addr(SR_TIME64 + 5); - x.status = READBACK_BASE + 4*8; - x.time64_secs_rb_imm = READBACK_BASE + 4*10; - x.time64_ticks_rb_imm = READBACK_BASE + 4*11; - x.compat_num_rb = READBACK_BASE + 4*12; - x.time64_secs_rb_pps = READBACK_BASE + 4*14; - x.time64_ticks_rb_pps = READBACK_BASE + 4*15; - x.dsp_tx_freq = sr_addr(SR_TX_DSP + 0); - x.dsp_tx_scale_iq = sr_addr(SR_TX_DSP + 1); - x.dsp_tx_interp_rate = sr_addr(SR_TX_DSP + 2); - x.dsp_tx_mux = sr_addr(SR_TX_DSP + 4); - x.dsp_rx[0].freq = sr_addr(SR_RX_DSP0 + 0); - x.dsp_rx[0].scale_iq = sr_addr(SR_RX_DSP0 + 1); - x.dsp_rx[0].decim_rate = sr_addr(SR_RX_DSP0 + 2); - x.dsp_rx[0].dcoffset_i = sr_addr(SR_RX_DSP0 + 3); - x.dsp_rx[0].dcoffset_q = sr_addr(SR_RX_DSP0 + 4); - x.dsp_rx[0].mux = sr_addr(SR_RX_DSP0 + 5); - x.dsp_rx[1].freq = sr_addr(SR_RX_DSP1 + 0); - x.dsp_rx[1].scale_iq = sr_addr(SR_RX_DSP1 + 1); - x.dsp_rx[1].decim_rate = sr_addr(SR_RX_DSP1 + 2); - x.dsp_rx[1].dcoffset_i = sr_addr(SR_RX_DSP1 + 3); - x.dsp_rx[1].dcoffset_q = sr_addr(SR_RX_DSP1 + 4); - x.dsp_rx[1].mux = sr_addr(SR_RX_DSP1 + 5); - x.gpio_io = GPIO_BASE + 0; - x.gpio_ddr = GPIO_BASE + 4; - x.gpio_tx_sel = GPIO_BASE + 8; - x.gpio_rx_sel = GPIO_BASE + 12; - x.atr_idle_txside = ATR_BASE + 0; - x.atr_idle_rxside = ATR_BASE + 2; - x.atr_intx_txside = ATR_BASE + 4; - x.atr_intx_rxside = ATR_BASE + 6; - x.atr_inrx_txside = ATR_BASE + 8; - x.atr_inrx_rxside = ATR_BASE + 10; - x.atr_full_txside = ATR_BASE + 12; - x.atr_full_rxside = ATR_BASE + 14; - x.rx_ctrl[0].stream_cmd = sr_addr(SR_RX_CTRL0 + 0); - x.rx_ctrl[0].time_secs = sr_addr(SR_RX_CTRL0 + 1); - x.rx_ctrl[0].time_ticks = sr_addr(SR_RX_CTRL0 + 2); - x.rx_ctrl[0].clear_overrun = sr_addr(SR_RX_CTRL0 + 3); - x.rx_ctrl[0].vrt_header = sr_addr(SR_RX_CTRL0 + 4); - x.rx_ctrl[0].vrt_stream_id = sr_addr(SR_RX_CTRL0 + 5); - x.rx_ctrl[0].vrt_trailer = sr_addr(SR_RX_CTRL0 + 6); - x.rx_ctrl[0].nsamps_per_pkt = sr_addr(SR_RX_CTRL0 + 7); - x.rx_ctrl[0].nchannels = sr_addr(SR_RX_CTRL0 + 8); - x.rx_ctrl[1].stream_cmd = sr_addr(SR_RX_CTRL1 + 0); - x.rx_ctrl[1].time_secs = sr_addr(SR_RX_CTRL1 + 1); - x.rx_ctrl[1].time_ticks = sr_addr(SR_RX_CTRL1 + 2); - x.rx_ctrl[1].clear_overrun = sr_addr(SR_RX_CTRL1 + 3); - x.rx_ctrl[1].vrt_header = sr_addr(SR_RX_CTRL1 + 4); - x.rx_ctrl[1].vrt_stream_id = sr_addr(SR_RX_CTRL1 + 5); - x.rx_ctrl[1].vrt_trailer = sr_addr(SR_RX_CTRL1 + 6); - x.rx_ctrl[1].nsamps_per_pkt = sr_addr(SR_RX_CTRL1 + 7); - x.rx_ctrl[1].nchannels = sr_addr(SR_RX_CTRL1 + 8); - x.tx_ctrl_num_chan = sr_addr(SR_TX_CTRL + 0); - x.tx_ctrl_clear_state = sr_addr(SR_TX_CTRL + 1); - x.tx_ctrl_report_sid = sr_addr(SR_TX_CTRL + 2); - x.tx_ctrl_policy = sr_addr(SR_TX_CTRL + 3); - x.tx_ctrl_cycles_per_up = sr_addr(SR_TX_CTRL + 4); - x.tx_ctrl_packets_per_up = sr_addr(SR_TX_CTRL + 5); - - return x; -} diff --git a/host/lib/usrp/usrp2/usrp2_regs.hpp b/host/lib/usrp/usrp2/usrp2_regs.hpp index 8390f065d..dbb78275b 100644 --- a/host/lib/usrp/usrp2/usrp2_regs.hpp +++ b/host/lib/usrp/usrp2/usrp2_regs.hpp @@ -18,90 +18,41 @@ #ifndef INCLUDED_USRP2_REGS_HPP #define INCLUDED_USRP2_REGS_HPP -typedef struct { - int misc_ctrl_clock; - int misc_ctrl_serdes; - int misc_ctrl_adc; - int misc_ctrl_leds; - int misc_ctrl_phy; - int misc_ctrl_dbg_mux; - int misc_ctrl_ram_page; - int misc_ctrl_flush_icache; - int misc_ctrl_led_src; - int time64_secs; // value to set absolute secs to on next PPS - int time64_ticks; // value to set absolute ticks to on next PPS - int time64_flags; // flags -- see chart below - int time64_imm; // set immediate (0=latch on next pps, 1=latch immediate, default=0) - int time64_tps; // ticks per second rollover count - int time64_mimo_sync; - int status; - int time64_secs_rb_imm; - int time64_ticks_rb_imm; - int time64_secs_rb_pps; - int time64_ticks_rb_pps; - int compat_num_rb; - int irq_rb; - int dsp_tx_freq; - int dsp_tx_scale_iq; - int dsp_tx_interp_rate; - int dsp_tx_mux; - struct{ - int freq; - int scale_iq; - int decim_rate; - int dcoffset_i; - int dcoffset_q; - int mux; - } dsp_rx[2]; - int gpio_base; - int gpio_io; - int gpio_ddr; - int gpio_tx_sel; - int gpio_rx_sel; - int atr_base; - int atr_idle_txside; - int atr_idle_rxside; - int atr_intx_txside; - int atr_intx_rxside; - int atr_inrx_txside; - int atr_inrx_rxside; - int atr_full_txside; - int atr_full_rxside; - struct{ - int stream_cmd; - int time_secs; - int time_ticks; - int clear_overrun; - int vrt_header; - int vrt_stream_id; - int vrt_trailer; - int nsamps_per_pkt; - int nchannels; - } rx_ctrl[2]; - int tx_ctrl_num_chan; - int tx_ctrl_clear_state; - int tx_ctrl_report_sid; - int tx_ctrl_policy; - int tx_ctrl_cycles_per_up; - int tx_ctrl_packets_per_up; -} usrp2_regs_t; - -extern const usrp2_regs_t usrp2_regs; //the register definitions, set in usrp2_regs.cpp and usrp2p_regs.cpp - -usrp2_regs_t usrp2_get_regs(void); - -//////////////////////////////////////////////////// -// Settings Bus, Slave #7, Not Byte Addressable! -// -// Output-only from processor point-of-view. -// 1KB of address space (== 256 32-bit write-only regs) - - -//#define MISC_OUTPUT_BASE 0xD400 -//#define TX_PROTOCOL_ENGINE_BASE 0xD480 -//#define RX_PROTOCOL_ENGINE_BASE 0xD4C0 -//#define BUFFER_POOL_CTRL_BASE 0xD500 -//#define LAST_SETTING_REG 0xD7FC // last valid setting register +//////////////////////////////////////////////////////////////////////// +// Define slave bases +//////////////////////////////////////////////////////////////////////// +#define ROUTER_RAM_BASE 0x4000 +#define SPI_BASE 0x5000 +#define I2C_BASE 0x5400 +#define GPIO_BASE 0x5800 +#define READBACK_BASE 0x5C00 +#define ETH_BASE 0x6000 +#define SETTING_REGS_BASE 0x7000 +#define PIC_BASE 0x8000 +#define UART_BASE 0x8800 +#define ATR_BASE 0x8C00 + +//////////////////////////////////////////////////////////////////////// +// Setting register offsets +//////////////////////////////////////////////////////////////////////// +#define SR_MISC 0 // 7 regs +#define SR_SIMTIMER 8 // 2 +#define SR_TIME64 10 // 6 +#define SR_BUF_POOL 16 // 4 + +#define SR_RX_FRONT 24 // 5 +#define SR_RX_CTRL0 32 // 9 +#define SR_RX_DSP0 48 // 7 +#define SR_RX_CTRL1 80 // 9 +#define SR_RX_DSP1 96 // 7 + +#define SR_TX_FRONT 128 // ? +#define SR_TX_CTRL 144 // 6 +#define SR_TX_DSP 160 // 5 + +#define SR_UDP_SM 192 // 64 + +#define U2_REG_SR_ADDR(sr) (SETTING_REGS_BASE + (4 * (sr))) ///////////////////////////////////////////////// // SPI Slave Constants @@ -120,6 +71,16 @@ usrp2_regs_t usrp2_get_regs(void); ///////////////////////////////////////////////// // Misc Control //////////////////////////////////////////////// +#define U2_REG_MISC_CTRL_CLOCK U2_REG_SR_ADDR(0) +#define U2_REG_MISC_CTRL_SERDES U2_REG_SR_ADDR(1) +#define U2_REG_MISC_CTRL_ADC U2_REG_SR_ADDR(2) +#define U2_REG_MISC_CTRL_LEDS U2_REG_SR_ADDR(3) +#define U2_REG_MISC_CTRL_PHY U2_REG_SR_ADDR(4) +#define U2_REG_MISC_CTRL_DBG_MUX U2_REG_SR_ADDR(5) +#define U2_REG_MISC_CTRL_RAM_PAGE U2_REG_SR_ADDR(6) +#define U2_REG_MISC_CTRL_FLUSH_ICACHE U2_REG_SR_ADDR(7) +#define U2_REG_MISC_CTRL_LED_SRC U2_REG_SR_ADDR(8) + #define U2_FLAG_MISC_CTRL_SERDES_ENABLE 8 #define U2_FLAG_MISC_CTRL_SERDES_PRBSEN 4 #define U2_FLAG_MISC_CTRL_SERDES_LOOPEN 2 @@ -131,22 +92,12 @@ usrp2_regs_t usrp2_get_regs(void); ///////////////////////////////////////////////// // VITA49 64 bit time (write only) //////////////////////////////////////////////// - /*! - * \brief Time 64 flags - * - * <pre> - * - * 3 2 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------------------------------------------------------+-+-+ - * | |S|P| - * +-----------------------------------------------------------+-+-+ - * - * P - PPS edge selection (0=negedge, 1=posedge, default=0) - * S - Source (0=sma, 1=mimo, 0=default) - * - * </pre> - */ +#define U2_REG_TIME64_SECS U2_REG_SR_ADDR(SR_TIME64 + 0) +#define U2_REG_TIME64_TICKS U2_REG_SR_ADDR(SR_TIME64 + 1) +#define U2_REG_TIME64_FLAGS U2_REG_SR_ADDR(SR_TIME64 + 2) +#define U2_REG_TIME64_IMM U2_REG_SR_ADDR(SR_TIME64 + 3) +#define U2_REG_TIME64_TPS U2_REG_SR_ADDR(SR_TIME64 + 4) +#define U2_REG_TIME64_MIMO_SYNC U2_REG_SR_ADDR(SR_TIME64 + 5) //pps flags (see above) #define U2_FLAG_TIME64_PPS_NEGEDGE (0 << 0) @@ -158,74 +109,43 @@ usrp2_regs_t usrp2_get_regs(void); #define U2_FLAG_TIME64_LATCH_NEXT_PPS 0 ///////////////////////////////////////////////// -// DSP TX Regs +// Readback regs //////////////////////////////////////////////// +#define U2_REG_STATUS READBACK_BASE + 4*8 +#define U2_REG_TIME64_SECS_RB_IMM READBACK_BASE + 4*10 +#define U2_REG_TIME64_TICKS_RB_IMM READBACK_BASE + 4*11 +#define U2_REG_COMPAT_NUM_RB READBACK_BASE + 4*12 +#define U2_REG_IRQ_RB READBACK_BASE + 4*13 +#define U2_REG_TIME64_SECS_RB_PPS READBACK_BASE + 4*14 +#define U2_REG_TIME64_TICKS_RB_PPS READBACK_BASE + 4*15 - /*! - * \brief output mux configuration. - * - * <pre> - * 3 2 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-------------------------------+-------+-------+-------+-------+ - * | | DAC1 | DAC0 | - * +-------------------------------+-------+-------+-------+-------+ - * - * There are N DUCs (1 now) with complex inputs and outputs. - * There are two DACs. - * - * Each 4-bit DACx field specifies the source for the DAC - * Each subfield is coded like this: - * - * 3 2 1 0 - * +-------+ - * | N | - * +-------+ - * - * N specifies which DUC output is connected to this DAC. - * - * N which interp output - * --- ------------------- - * 0 DUC 0 I - * 1 DUC 0 Q - * 2 DUC 1 I - * 3 DUC 1 Q - * F All Zeros - * - * The default value is 0x10 - * </pre> - */ - +///////////////////////////////////////////////// +// DSP TX Regs +//////////////////////////////////////////////// +#define U2_REG_DSP_TX_FREQ U2_REG_SR_ADDR(SR_TX_DSP + 0) +#define U2_REG_DSP_TX_SCALE_IQ U2_REG_SR_ADDR(SR_TX_DSP + 1) +#define U2_REG_DSP_TX_INTERP_RATE U2_REG_SR_ADDR(SR_TX_DSP + 2) +#define U2_REG_DSP_TX_MUX U2_REG_SR_ADDR(SR_TX_DSP + 4) ///////////////////////////////////////////////// // DSP RX Regs //////////////////////////////////////////////// +#define U2_REG_DSP_RX_HELPER(which, offset) ((which == 0)? \ + (U2_REG_SR_ADDR(SR_RX_DSP0 + offset)) : \ + (U2_REG_SR_ADDR(SR_RX_DSP1 + offset))) - /*! - * \brief input mux configuration. - * - * This determines which ADC (or constant zero) is connected to - * each DDC input. There are N DDCs (1 now). Each has two inputs. - * - * <pre> - * Mux value: - * - * 3 2 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-------+-------+-------+-------+-------+-------+-------+-------+ - * | |Q0 |I0 | - * +-------+-------+-------+-------+-------+-------+-------+-------+ - * - * Each 2-bit I field is either 00 (A/D A), 01 (A/D B) or 1X (const zero) - * Each 2-bit Q field is either 00 (A/D A), 01 (A/D B) or 1X (const zero) - * - * The default value is 0x4 - * </pre> - */ +#define U2_REG_DSP_RX_FREQ(which) U2_REG_DSP_RX_HELPER(which, 0) +#define U2_REG_DSP_RX_SCALE_IQ(which) U2_REG_DSP_RX_HELPER(which, 1) +#define U2_REG_DSP_RX_DECIM(which) U2_REG_DSP_RX_HELPER(which, 2) +#define U2_REG_DSP_RX_MUX(which) U2_REG_DSP_RX_HELPER(which, 5) //////////////////////////////////////////////// -// GPIO, Slave 4 +// GPIO //////////////////////////////////////////////// +#define U2_REG_GPIO_IO GPIO_BASE + 0 +#define U2_REG_GPIO_DDR GPIO_BASE + 4 +#define U2_REG_GPIO_TX_SEL GPIO_BASE + 8 +#define U2_REG_GPIO_RX_SEL GPIO_BASE + 12 // each 2-bit sel field is layed out this way #define U2_FLAG_GPIO_SEL_GPIO 0 // if pin is an output, set by GPIO register @@ -234,35 +154,43 @@ usrp2_regs_t usrp2_get_regs(void); #define U2_FLAG_GPIO_SEL_DEBUG_1 3 // if pin is an output, debug lines from FPGA fabric /////////////////////////////////////////////////// -// ATR Controller, Slave 11 +// ATR Controller //////////////////////////////////////////////// - +#define U2_REG_ATR_IDLE_TXSIDE ATR_BASE + 0 +#define U2_REG_ATR_IDLE_RXSIDE ATR_BASE + 2 +#define U2_REG_ATR_INTX_TXSIDE ATR_BASE + 4 +#define U2_REG_ATR_INTX_RXSIDE ATR_BASE + 6 +#define U2_REG_ATR_INRX_TXSIDE ATR_BASE + 8 +#define U2_REG_ATR_INRX_RXSIDE ATR_BASE + 10 +#define U2_REG_ATR_FULL_TXSIDE ATR_BASE + 12 +#define U2_REG_ATR_FULL_RXSIDE ATR_BASE + 14 /////////////////////////////////////////////////// // RX CTRL regs /////////////////////////////////////////////////// -// The following 3 are logically a single command register. -// They are clocked into the underlying fifo when time_ticks is written. -//#define U2_REG_RX_CTRL_STREAM_CMD _SR_ADDR(SR_RX_CTRL + 0) // {now, chain, num_samples(30) -//#define U2_REG_RX_CTRL_TIME_SECS _SR_ADDR(SR_RX_CTRL + 1) -//#define U2_REG_RX_CTRL_TIME_TICKS _SR_ADDR(SR_RX_CTRL + 2) - -//#define U2_REG_RX_CTRL_CLEAR_STATE _SR_ADDR(SR_RX_CTRL + 3) -//#define U2_REG_RX_CTRL_VRT_HEADER _SR_ADDR(SR_RX_CTRL + 4) // word 0 of packet. FPGA fills in packet counter -//#define U2_REG_RX_CTRL_VRT_STREAM_ID _SR_ADDR(SR_RX_CTRL + 5) // word 1 of packet. -//#define U2_REG_RX_CTRL_VRT_TRAILER _SR_ADDR(SR_RX_CTRL + 6) -//#define U2_REG_RX_CTRL_NSAMPS_PER_PKT _SR_ADDR(SR_RX_CTRL + 7) -//#define U2_REG_RX_CTRL_NCHANNELS _SR_ADDR(SR_RX_CTRL + 8) // 1 in basic case, up to 4 for vector sources +#define U2_REG_RX_CTRL_HELPER(which, offset) ((which == 0)? \ + (U2_REG_SR_ADDR(SR_RX_CTRL0 + offset)) : \ + (U2_REG_SR_ADDR(SR_RX_CTRL1 + offset))) + +#define U2_REG_RX_CTRL_STREAM_CMD(which) U2_REG_RX_CTRL_HELPER(which, 0) +#define U2_REG_RX_CTRL_TIME_SECS(which) U2_REG_RX_CTRL_HELPER(which, 1) +#define U2_REG_RX_CTRL_TIME_TICKS(which) U2_REG_RX_CTRL_HELPER(which, 2) +#define U2_REG_RX_CTRL_CLEAR(which) U2_REG_RX_CTRL_HELPER(which, 3) +#define U2_REG_RX_CTRL_VRT_HDR(which) U2_REG_RX_CTRL_HELPER(which, 4) +#define U2_REG_RX_CTRL_VRT_SID(which) U2_REG_RX_CTRL_HELPER(which, 5) +#define U2_REG_RX_CTRL_VRT_TLR(which) U2_REG_RX_CTRL_HELPER(which, 6) +#define U2_REG_RX_CTRL_NSAMPS_PP(which) U2_REG_RX_CTRL_HELPER(which, 7) +#define U2_REG_RX_CTRL_NCHANNELS(which) U2_REG_RX_CTRL_HELPER(which, 8) /////////////////////////////////////////////////// // TX CTRL regs /////////////////////////////////////////////////// -//#define U2_REG_TX_CTRL_NUM_CHAN _SR_ADDR(SR_TX_CTRL + 0) -//#define U2_REG_TX_CTRL_CLEAR_STATE _SR_ADDR(SR_TX_CTRL + 1) -//#define U2_REG_TX_CTRL_REPORT_SID _SR_ADDR(SR_TX_CTRL + 2) -//#define U2_REG_TX_CTRL_POLICY _SR_ADDR(SR_TX_CTRL + 3) -//#define U2_REG_TX_CTRL_CYCLES_PER_UP _SR_ADDR(SR_TX_CTRL + 4) -//#define U2_REG_TX_CTRL_PACKETS_PER_UP _SR_ADDR(SR_TX_CTRL + 5) +#define U2_REG_TX_CTRL_NUM_CHAN U2_REG_SR_ADDR(SR_TX_CTRL + 0) +#define U2_REG_TX_CTRL_CLEAR_STATE U2_REG_SR_ADDR(SR_TX_CTRL + 1) +#define U2_REG_TX_CTRL_REPORT_SID U2_REG_SR_ADDR(SR_TX_CTRL + 2) +#define U2_REG_TX_CTRL_POLICY U2_REG_SR_ADDR(SR_TX_CTRL + 3) +#define U2_REG_TX_CTRL_CYCLES_PER_UP U2_REG_SR_ADDR(SR_TX_CTRL + 4) +#define U2_REG_TX_CTRL_PACKETS_PER_UP U2_REG_SR_ADDR(SR_TX_CTRL + 5) #define U2_FLAG_TX_CTRL_POLICY_WAIT (0x1 << 0) #define U2_FLAG_TX_CTRL_POLICY_NEXT_PACKET (0x1 << 1) |