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-rw-r--r--host/utils/rfnoc_blocktool/templates/Makefile19
1 files changed, 9 insertions, 10 deletions
diff --git a/host/utils/rfnoc_blocktool/templates/Makefile b/host/utils/rfnoc_blocktool/templates/Makefile
index ca397bf7d..7b151e3b9 100644
--- a/host/utils/rfnoc_blocktool/templates/Makefile
+++ b/host/utils/rfnoc_blocktool/templates/Makefile
@@ -7,15 +7,20 @@
#-------------------------------------------------
# Top-of-Makefile
#-------------------------------------------------
-# Define BASE_DIR to point to the "top" dir
-BASE_DIR = $(abspath ../../../../top)
+# Define BASE_DIR to point to the "top" dir. Note:
+# UHD_FPGA_DIR must be passed into this Makefile.
+ifndef UHD_FPGA_DIR
+$(error "UHD_FPGA_DIR is not set! Must point to UHD FPGA repository!")
+endif
+BASE_DIR = $(UHD_FPGA_DIR)/usrp3/top
# Include viv_sim_preample after defining BASE_DIR
include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
#-------------------------------------------------
# Design Specific
#-------------------------------------------------
-# Include makefiles and sources for the DUT and its dependencies
+# Include makefiles and sources for the DUT and its
+# dependencies.
include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs
include $(BASE_DIR)/../lib/rfnoc/utils/Makefile.srcs
include Makefile.srcs
@@ -23,21 +28,15 @@ include Makefile.srcs
DESIGN_SRCS += $(abspath ${"\\"}
$(RFNOC_CORE_SRCS) ${"\\"}
$(RFNOC_UTIL_SRCS) ${"\\"}
-$(RFNOC_BLOCK_${config['module_name'].upper()}_SRCS) ${"\\"}
+$(RFNOC_OOT_SRCS) ${"\\"}
)
#-------------------------------------------------
# Testbench Specific
#-------------------------------------------------
-include $(BASE_DIR)/../sim/rfnoc/Makefile.srcs
-
SIM_TOP = rfnoc_block_${config['module_name']}_tb
-
SIM_SRCS = ${"\\"}
$(abspath rfnoc_block_${config['module_name']}_tb.sv) ${"\\"}
-$(SIM_RFNOC_SRCS)
-
-# MODELSIM_USER_DO = $(abspath wave.do)
#-------------------------------------------------
# Bottom-of-Makefile